Gradient products, implemented in the UMC flow, poised to help designs operate within temperature specifications
With increasing performance and circuit densities, system-on-a-chip (SoC) and custom designs are experiencing bigger temperature variations across the die. Gradient's three-dimensional thermal analysis technology, which is fine-grain, accurate and scalable for the latest chip designs, can be integrated into UMC's existing nanometer design flows. Gradient's products are designed to help users accurately identify possible thermal violations and to more accurately determine the thermal effects on critical aspects such as timing, leakage and electro-migration -- thermal impacts that can be missed with today's uniform die-temperature methodology.
"Gradient's technology is poised to help designers ensure that their silicon operates within temperature specs, and thus makes a good addition to our portfolio," said Dr. Long-Ching Yeh, vice president of UMC's EDA tool and DFM support.
Gradient is focused on providing mutual customers with access to design kits and flows for various process nodes, including UMC's proven 65nm process. The first flow, based on Gradient's FireBolt product, has been applied to a test chip produced on UMC's 90nm process node. A future effort focuses on 65nm design flow development, including thermal impact on timing.
"By taking into account UMC's foundry data, detailed package characteristics, power values and design layout information, a detailed thermal profile of the design can be quickly produced for all the operating modes of the chip, in order to identify temperature hotspots and simulate their impact," said Edmund Cheng, president and CEO of Gradient. "We are currently in discussions with a number of fabless companies that are interested in thermal verification, and require thermal techfile data from foundries. Thus we are excited to work with UMC to offer our technology as part of their flow."
Through collaboration with UMC, Gradient is developing thermal-aware design flows to build upon existing "worst-case temperature" design approaches. The worst-case temperature approach, along with other process on-chip variations (OCV), can result in very expensive design margins. By providing access to the deterministic picture for on-chip temperature, designers can better guide the placement of sensitive circuit elements, such as thermal sensors.
Gradient Design Automation provides thermal analysis solutions for the power-intensive and temperature-sensitive integrated circuits (ICs) that are used in the automotive, computer, hand-held, and networking application segments. The Gradient products integrate easily into existing IC design flows and provide a rich set of visual analysis capabilities. For the first time, designers can have visibility into the fine-grain temperature profile throughout the design process, locate temperature hotspots, and simulate their impact on the design parameters. Gradient is located in Santa Clara, California. For more information, visit www.gradient-da.com.
Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward looking within the meaning of the U.S. Federal Securities laws, including statements about future outsourcing, wafer capacity, technologies, business relationships and market conditions. Investors are cautioned that actual events and results could differ materially from these statements as a result of a variety of factors, including conditions in the overall semiconductor market and economy; acceptance and demand for products from UMC; and technological and development risks.
PR for Gradient: Cayenne Communication LLC
Linda Marchant, Email Contact, 919-451-0776