Synopsys & SystemVerilog Verification Methodology Manual (VMM)
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Synopsys & SystemVerilog Verification Methodology Manual (VMM)


Over recent months Synopsys has issued several press releases about their support for SystemVerilog. On March 20th they announced support for the SystemVerilog language throughout its suite of design and verification products. On the same day they announced introduced SystemVerilog verification IP support for its VCS Verification Library and a new native SystemVerilog parser in their Formality equivalence checker. On July 26 the firm announced that it has donated a library of advanced SystemVerilog assertion checkers defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog to Accellera. Recently, I had an opportunity to discuss these with George Zafiropoulos, VP of Marketing Synopsys Verification Group

Would you provide us with a brief biography?
I have been here at Synopsys since the middle of last year, just about one year. My role here at Synopsys is VP of Marketing for the verification business. Prior to that I spent about 9 years running verification platform marketing at Cadence and at Quickturn Design Systems before they were acquired by Cadence. Before that I was at this little startup company called Synopsys from 1989 to 1996 also in marketing. Before that I was at other EDA companies. I have been in the EDA business far too long, for 20 something years, in verification for most of that time.

What do you see as the purpose of Marketing, as your role at Synopsys?
A lot of our role is to help to understand what the customers' requirements are and where the industry is going from a strategic point of view, to help the company understand what our customers' needs are, and to make sure we can meet those needs. Also to help communicate to our customers and potential customers about the value of what we have to offer.

How do you accomplish that?
In understanding customers' needs I think it is spending time with our users and customers to understand what their challenges are, understand what is working well in their current verification environment and where they can use some help. Sometimes that help turns out to be education and knowledge, sometimes it is methodology, sometimes IP and sometimes it is technology in the form of software applications to help them do a better job in verification. So really, it's spending a lot of time with users is the biggest source of information.

In terms of communicating what we've got is a traditional communication challenge - articles, publications, trade shows and so forth. Increasingly publications are becoming a major component of that. We spend a lot of time in one-on-one with our customers. So while we try to understand what their issues are, we are also educating them on what we have to offer.

How was the Design Automation Conference for you this year?
Overall DAC was quite good for us. I spent my time talking with customers about verification related things. Verification is a pretty hot topic. There was a lot of interest. We sponsored a luncheon event about System Verilog. We had a great set of panelists from several of our users. They talked about the current state of adoption of SystemVerilog and they are using that and the impact of that. That was really good. We had a very big turn out at this event. We also sponsored a breakfast for the Accellera standard organization. A lot of that was discussion around SystemVerilog adoption. That was a sellout.

What were the recent press releases all about?
The first press release on July 18th was about the momentum for our methodology. The second was on July 26th about a donation we've made of SystemVerilog Assertion Libraries to Accellera.

The top story is industry momentum is building about the methodology that we've developed between Synopsys and ARM for the deployment of verification methodology for SystemVerilog based designs. The point is that we've seen substantial interest in the methodology we've developed. The supporting proof points for that are: We've got several endorsements. We've seen a big demand for the publication that we've jointly put out which is the Verification Methodology Manual (VMM) for SystemVerilog. We've got lots of users downloading our library that supports the VMM. And we've seen a growing ecosystem around publications and training courses being offered in support of our methodology.

How much does the book cost?
$129. If you want to but it on Amazon, you can get it for less than that. In the spirit of full disclosure, they sent me a book for free. The plot is familiar but character development is weak.

What were the user endorsements?
As part of the press release we identified there companies which were publicly acknowledging the verification methodology: AMR, Vitesse and Alacritech. ARM of course being a co-author of the publication you would expect that they would endorse it. Keith Clark, who ran a lot of the processor development for ARM, is a key senior guy in the ARM organization. He says “The VMM methodology is being followed with great success by many companies in the electronic design industry. A keen interest for ARM is to make sure that their designers designing in ARM technology to their silicon have a solid methodology for doing design and verification because that is becoming a really big headache. They are a pretty big proponent of SystemVerilog because they see that as having one industry standard language for design and verification as a really good thing. They have been a big proponent of working closely with us for a number of years now on the standardization of SystemVerilog.

Clearly the book was not written over a weekend. What was the motivation that sparked the effort and what was the size of that effort?
The methodology you see in VMM is a combination of a lot of guys with a lot of verification project experience. Combination of things. One element that is set into this is that we developed a methodology called RVM. RVM has been deployed by a lot of our customers primarily in the Vera testbench language. One of the key co-authors of the book is Janick Bergeron. Janick was one of the principals of a company called Qualis whose primary consulting business was verification. Janick was personally involved with many, many companies doing advanced verification. Synopsys acquired Qualis (April 2003). That brought in a lot of additional verification expertise. That was a big contribution to the development of the methodology. Thirdly, working with ARM. They have a lot of verification expertise working around not just verifying their cores but having to support so many customers doing designs that are based upon ARM that they felt that having a standardized verification methodology that was well understood and well documented and well supported by the technology would really streamline their customers, our joint customers, ability to get designs done. The VMM was developed over the course of a year, a year and a half as we developed into a publication that came out as VMM. The ground work for that has been accumulating for several years in experiences at Synopsys, Qualis and ARM.

What does RVM stand for?
Reuse Verification Methodology. RVM has been deployed by numerous customers over the years but not around SystemVerilog per se. It was really more around Vera. I am sure that you know that SystemVerilog testbench a lot of that technology was original donation from Synopsys from Vera. So it was a very natural extension.

There are a couple of other endorsements from Vitesse and Alacritech with very similar points of view from users of the methodology. There are two other public endorsements that were not part of the press release. Ross Video adopted our VCS NTV technology. NTV native testbench which means the testbench compiles and runs natively in the simulation kernel which gives high performance. Ross adopted our technology for its performance capability and because of the VMM methodology. Similarly form S3 (Silicon Software Systems) also using VCS & NTV deploying it in a verification methodology as prescribed in the book.

We originally released the first edition of VMM in September of last year. Today over 3,500 copies have been sold which is quite good. According to Carl Harris the Springer editor on the VMM book this is one of the fastest selling EDA books. Maybe by NY Times best seller list standards, 3500 copies don't sound like that many but in EDA it is pretty big, so much so that we decided to produce a Japanese version. That was published in February. The Japanese version of VMM while it is based on the English version we also worked with about a dozen Japanese companies, electronic design companies, consulting companies and others as well as the STARC organization. The reason for that is to collaborate with a lot of our end users to make sure that they understood and could comment on this version of VMM, We are looking at what other languages might be appropriate.

Have you picked one? Swedish? Chinese?
At this point we haven't gone into production. It is likely we will do a Chinese version but that has not been decided yet. The English version is acceptable in most of the other countries. We have a tremendous interest in India for example. The English version is appropriate for India. But doing a Chinese version would probably make sense.

One of the things we have seen over the last few months is not only the popularity of our publication but interestingly enough several other authors have created publications in support of VMM. On the product side our own products obviously support VMM - simulation, testbench, verification IP library all support VMM as you would assume. On the training side Synopsys offers methodology training courses based on the VMM book. We see others rallying around support for VMM. The University of California approached us. They are doing a 10 week course about verification. They have selected VMM as the basic text for the course. They will be announcing that publicly. We are happy they choose VMM. It shows a groundswell of interest around VMM as the methodology of choice. We are excited to work with them on that. The third thing is Doulos, a training consulting company. They have come out with their own training course based on VMM as has Southerland HDL.

Janick Bergeron, one of the coauthors, has just published a follow-on text called Writing Testbenches for SystemVerilog. Also SystemVerilog for Verification is a new book by Chris Spear, independently written and published that is coming at it from a point of view to introduce the language. There is also Pragmatic Approach to VMM Adoption and VMM for SystemVerilog for Design.

It is interesting to us as VMM started to be adopted by users you saw a groundswell of interest in the follow-on ecosystem of training and these publications. There are other publications in the works that we can't talk about that we are aware of. We very much encourage that because the side spread use of the methodology benefits the users greatly. To the extent there is more and more supporting material, knowledge and experts who can deploy it, the better.

For reference we have a specific website around SystemVerilog for the whole design flow which can be found at

At our users group meeting (SNUG) we announced the first full production flow for SystemVerilog which incorporates all of these technologies: simulation, testbench, verification IP library, design rule checking, formal analysis, synthesis design compiler and formal equivalence checking with Formality. You can do a full design and verification flow based upon SystemVerilog from Synopsys.

Synopsys Complete SystemVerilog Flow

To what extent can VMM be used with tools from other vendors?
Very good question! There are two questions. The first is that independent of SystemVerilog how applicable are the concepts in VMM? Without regard to SystemVerilog the concepts in the manual are really universal. They can be applied to different verification languages as well as different vendor tools. Think of this as a base conceptual methodology. There is a lot of good information in the methodology as we've defined it. The next part of the question is that since all the examples are based around SystemVerilog and it is really geared to SystemVerilog in the book, how transportable is it. The answer is really generic. The concepts in the book are pretty tool independent. In the book we specify a class library that you can use to support the methodology. We have a version of that which is available for download from our website at no charge to our customers. It has been tested with our tools. It may well be portable to other tools but we QA tested it with our own tools. We also know that there are end users out there who have developed their own class libraries to make sure that they are compatible with whatever tools they happen to be using. I think this one of the reasons why the book has been so popular. The concepts are really broad. There is no reason that you could not apply the same methodology to other tools. The obvious advantage is that if you use the Synopsys tools, they are guaranteed to work off-the-shelf. Of course we believe that we have the best tool set which gives the best performance and best functionality. Obviously we would like you to use Synopsys.

Does anyone else offer a complete flow based upon SystemVerilog?
No! We have by far the most complete flow today. Everybody else is scrambling around trying to fill in the holes they've got because they see the industry momentum clearly in the direction of SystemVerilog. Some other technology suppliers are very enthusiastic about SystemVerilog others are not but they all pretty much see the writing on the wall where the industry is going. We are the first to market with the most complete flow and with the most expertise.

What is the alternative to SystemVerilog?
Historically different design teams have used all manner of languages for design and verification. If you go back 5 to 10 years, a lot of companies have been using traditional HDL, Verilog and VHDL. A lot of companies used some level of C for design and architecture and Verilog or HDL for hardware and maybe C for testbench. We've seen the use of languages like Vera and some C. Probably the most widely used hardware language in the industry up to now has been Vera. SystemVerilog Testbench is really an evolution of Vera. We've taken it from essentially a Synopsys language and donated it to the industry. A lot of companies have rallied around that as an industry standard. Of course it is the e language for Synopsys.

What market share or percent of designs does SystemVerilog have? Is there any quantitative measurement of penetration?
I really don't have percentages. But I can give you a fell for what we see. We see SystemVerilog being adopted in phases over the last few years. The first part of SystemVerilog to be widely used is assertions, SVA. You really started to see that take off over the last 18 to 24 months, so much so that we don't track the number of designs using SystemVerilog.

It's hundreds of thousands. It's pretty much become the predominant assertion modeling language. The next wave you see starting is in the testbench area. SystemVerilog Testbench is in the beginning of mass adoption now. That's really the reason why you are seeing this groundswell of interest from the market.

We are starting to see more adoption of SystemVerilog for design. I think we will see a significant uptake over the next year or two. There are a lot of teams using SystemVerilog design constructs. I think we will see that mainstream over the next year or so.

Your website speaks of 5x performance improvement with SystemVerilog. Compare to what?
Compared to using a Verilog simulation and another HDL like Specman with e. We've done a lot of benchmarks and worked with a lot of companies who are interested in having an advanced testbench environment, really looking for industry standards and performance. We've seen a lot of those Specman users looking at moving to SystemVerilog, in particular with NTV because of standardization, the side adoption of SystemVerilog and the performance we offer. Our NTV technology allows us to get significantly greater performance than other implementation of testbench based on C. The reason for that is that the testbench that is being executed is executed in a single environment unlike a lot of other tools where there are other testbench and simulator tools that We actually compile into a single executable. We have that performance advantage.

To what extent are testbenches design specific? Is there any legacy? Is there any penalty other than learning curve in moving forward to a new language?
You tend to find a wide variety of where design teams are in that process. You find there are some design teams that have no legacy. They are really fresh. They are a new team beginning a new project. They really don't need any stuff developed in the past. They have the luxury of picking whatever is best. The vast majority of companies and design teams are going SystemVerilog because they see that's the obvious path. A little more complicated situation is where a project is doing a new version of a design with a legacy testbench. Many times there are thousands of lines of code. The verification or design team doesn't want to throw it away. In our testbench environment we can handle Verilog, VHLD or C kinds of testbenches at the same time. We see a lot of designs teams that were VHDL based where they see the future of SystemVerilog. They have some verification IP models in HDL. Our VCS + NTV products will support running not only all the SystemVerilog but also run their VHDL, Verilog or C code. It is really important to be able to support that legacy and at the same time give them the industry standard new language and the performance they would like to get out of it.

What about the donation to Accellera?
Editor: Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies. Over the years, Accellera has developed eight standards that have been ratified by the IEEE. Accellera's recent successes in advanced design and verification language standards include SystemVerilog and the Property Specification Language (PSL)

We've donated our assertion library to Accellera. I don't know how familiar you are with checker or assertion library concept. A lot of teams will write assertions from scratch using a language like SVA (SystemVerilog Assertions). What is really handy is to be able to have a library of checkers at a high level kind of like macros where you can instantiate a checker to check a particular common kind of condition. Those sort of things are usually built up in the form of a library. To date many different technology suppliers like Synopsys have had their own library of checkers. We wanted to further the broad adoption of SystemVerilog. Based upon feedback from our customers, we took our assertion library and donated it to Accellera.

There is a current library called OVL (Open Verilog Library). The OVL library is totally portable and is used across anybody's simulation platform. That's sort of the common denominator today in assertion libraries. We've donated assertions to Accellera. It will be up to Accellera to decide how they want to deliver those assertions. They will have the option of being able to create an extension to the current OVL library or perhaps a new library. Whatever they decide to do, the important point is that there is a richer set of library constructs that design teams can pick from. And being that these are Accellera endorsed and delivered standard libraries, they would likely be portable across anybody's tools.

What was Synopsys' motivation for this generous donation?
We do two types of things. We do things that make life better for our customers which may or may not directly help us. There are things that we do that are really in the spirit of helping our customers without regard for ourselves. Then there are things that we do to maximize our opportunity within the marketplace. Things like identifying industry standards and donating technology. We do this all the time. We do that because that's what our users believe is very important to have. If we contribute that donation, we make their lives better. We believe our unique advantage is in how well we execute around those donations. The fact that we would help create the SystemVerilog language as an industry standard that helps all of our customers but it also helps all of our competitors to build to a standard language. Our advantage we believe is that we can come back and say now that you have chosen to go down the path of an industry standard language or use an industry standard library like these extensions to OVL, our implementation is better than anybody else. Ours is faster, more robust, better integrated. Ours is supported by verification IP. We don't think that proprietary languages, proprietary APIs, proprietary environments are the way to go. Users don't like that. It is not in their best interest. We appeal to our end users by helping them get to the point where they can use really good standard techno logy. Then they can pick and choose what is the very best implementation of that. We are confident that we have that.

Is there anything on the product front for SystemVerilog coming up for Synopsys?
The most recent announcement was providing SystemVerilog across the full flow with Design Compiler, Formality as well as our verification platform. We are always doing more things. There will certainly be more technology, more in the way of product technology, more in the way of verification IP, more in the way of methodology to come in the near future. We will have to get back to you when we are ready to talk to you about those things.

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