Verific HDL Component Software Acts as Front End to MVSIM
This support for the Verilog and VHDL languages is made possible by hardware description level (HDL) Component Software from Verific Design Automation that serves as the front end to MVSIM. ArchPro initially licensed the VHDL parser and static elaborator, and recently added Verilog Component Software. Verific's HDL component software packages, delivered to ArchPro as source code, are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms for both 32- and 64-bit compilers.
ArchPro CEO and chairman, Pratap Reddy, notes: "When looking for software to serve as a front end to EDA design tools, Verific is the first name that comes up every time. And, for good reason -- its products are easy to integrate and offer good value. With Verific serving as MVSIM's front end, users can be assured quality and high performance verification."
MVSIM enables users to make system-level architectural decisions at RTL related to multi-voltage techniques including dynamic voltage scaling, power gating, and back bias. It works with popular simulators like ModelSim, NC-Sim, and VCS enabling users to verify multi-voltage designs at the RTL level. "ArchPro is serving a previously unmet need in the market with its low-power, multi-voltage simulator," comments Michiel Ligthart, Verific's chief operating officer. "It gives us great pride to be part of a solution that will help designers meet the demanding 90- and 65nm power challenges."
ArchPro provides EDA products to meet low-power and multi-voltage design challenges facing 90/65nm SoC designers. Having launched many of the world's first EDA products for power-managed, multi-voltage, low-power design environments that allow for design simulation, verification and implementation prior to silicon spins, ArchPro is paving the way toward reducing cost, risk, and time to market for chip designers. Products support all major complementary IC / SoC design technologies. Privately held ArchPro is based in San Jose, Calif. www.archpro-da.com.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: http://www.verific.com.
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