Toshiba Adopts Azuro's PowerCentric Clock Tree Synthesis and Optimization Solution
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Toshiba Adopts Azuro's PowerCentric Clock Tree Synthesis and Optimization Solution

SANTA CLARA, Calif.—(BUSINESS WIRE)—May 31, 2007— Azuro, Inc., the provider of advanced clock implementation tools for nanometer (nm) chip design, today announced that Toshiba America Electronics Components, Inc. (TAEC) has adopted Azuro's PowerCentric(TM) clock tree synthesis and optimization solution. TAEC is augmenting its existing design flow with PowerCentric in order to meet the aggressive demands of low-power clock implementation at 90nm and below.

"Power has become one of the critical drivers for TAEC customers. In our evaluation, PowerCentric delivered 15 to 25 percent reduction in power consumption compared to our existing implementation with minimum impact on design size or performance," said Atsushi Watanabe, vice president Design Solutions at TAEC. "Since many of our customers have designs that sit on the cusp of a power/performance envelope, this power reduction could make possible an array of low-cost, package solutions.

"PowerCentric integrates smoothly into our low-power design flow as an alternative to our current clock tree synthesis capability. In addition to its power reduction benefits, the product also offers extensive features to analyze our clock trees and power dissipation, which we believe will significantly enhance the productivity of our engineers on designs containing complex clock topologies."

Azuro's PowerCentric operates as a complete replacement for clock tree synthesis within digital design flows, comprehensively addressing power, timing, and variability within one unified optimization environment. PowerCentric brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis, and statistical average-case dynamic power analysis, to deliver a completely unified clock implementation solution for advanced nanometer designs.

"PowerCentric treats clock tree synthesis like a physical optimization problem," said Ashutosh Mauskar, vice president of product marketing for Azuro. "Timing, power, routability, area, and variability are the value metrics that really matter to a designer, but traditional clock tree synthesis engines ignore these underlying value metrics and just build buffer trees according to a set of clock tree synthesis constraints. PowerCentric is substantially more than just another clock tree synthesis tool. It builds clock trees, but it also makes significant changes to logic and cell placement at the same time. TAEC's adoption of PowerCentric further validates PowerCentric's clock tree synthesis and optimization technology leadership. We look forward to working with TAEC."

About Azuro


Azuro, Inc. is a provider of advanced clock implementation tools for nanometer chip design. Azuro's flagship product, PowerCentric(TM), operates as a complete replacement for clock tree synthesis within digital design flows, comprehensively addressing power, timing, and variability within one unified optimization environment. Founded in 2002, the privately held company is headquartered in Santa Clara, California, with R&D offices in Cambridge, UK.

Azuro's technology has been in production use since early 2004 where it has been consistently proven to deliver significant reductions in total chip power consumption without any impact on chip size or performance. For further information, visit www.azuro.com or call (408) 970-8200.

Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

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Azuro, Inc.
Jennifer Bilsey, 408-970-8205
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Michelle Clancy, 252-940-0981
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