Zenasis Technologies Forms Technical Advisory Board
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Zenasis Technologies Forms Technical Advisory Board

CAMPBELL, Calif.--(BUSINESS WIRE)--Nov. 12, 2002 -- Zenasis Technologies, Inc., an electronic design automation (EDA) startup delivering next-generation integrated circuit (IC) optimization software, today announced its Technical Advisory Board (TAB), that has been guiding its technology direction since its inception in Oct 2000.

The group, which is meeting today, holds quarterly sessions at the Zenasis corporate headquarters in Campbell, Calif. Jacob Abraham, Cockrell Family Regents chair in the Department of Electrical and Computer Engineering at the University of Texas at Austin, serves as the TAB chairman.

Other members are: John P. Hayes, Claude E. Shannon professor of Engineering Science at the University of Michigan; Masahiro Fujita, professor of Electronic Engineering at University of Tokyo; Kaushik Roy, professor of Electrical and Computer Engineering at Purdue University; and Sachin Sapatnekar, professor in the ECE department of University of Minnesota at Minneapolis.

Debashis Bhattacharya, Zenasis' chief technical officer (CTO), who oversees the TAB, says, "We have assembled some of the brightest minds in high performance and low-power IC design and analysis, to form our TAB. The members were selected for their expertise to help us define our next-generation technology and products. We expect their contributions to keep us on the cutting edge of IC design and optimization."

Zenasis is developing a new technology that simultaneously performs analysis, design and implementation at the gate and transistor levels. While physical optimization tools operate at the placed-gate level, Zenasis hybrid optimization goes beyond placed gates into the transistor-level, unfolding a whole new array of options for design optimization.

About Zenasis Technologies, Inc.

Zenasis Technologies, Inc., is an electronic design automation (EDA) company delivering next-generation integrated circuit (IC) design optimization technology for cell-based design. Its context-specific "hybrid optimization" operates at the gate and transistor levels for a given design placement, and empowers designers to simultaneously improve performance, power, area and routing. The Zenasis team has a mix of experience in EDA, semiconductor and high-performance design industries. Founded in 2000, it has received a total of $10 million venture funding. Corporate headquarters is located at: 1671 Dell Ave., Suite 206, Campbell, Calif., 95008. Telephone: (408) 364-2002. Facsimile: (408) 364-2236. Email: Email Contact. Online information is found at its website: http://www.zenasis.com

Zen is a trademark of Zenasis Technologies, Inc. Zenasis acknowledges trademarks or registered trademarks of other organizations for their respective products and services.


Contact:
     Public Relations for Zenasis Technologies
     Nanette Collins, 617/437-1822
     
Email Contact



Source: Zenasis Technologies