Si2 Announces Release of Common Power Format Version 1.1
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Si2 Announces Release of Common Power Format Version 1.1

AUSTIN, Texas—(BUSINESS WIRE)—September 23, 2008— Today the Silicon Integration Initiative (Si2) announced release of the Common Power Format (CPF) Version 1.1, incorporating major enhancements to the widely adopted low-power intent format. CPF 1.1 was approved by the Low Power Coalition (LPC).

Ameesh Desai, Si2 Board Chair and Senior Director of Design Tools and Methodology at LSI said, I am pleased with the rapid progress of the CPF. Efficient power utilization has become a primary need for electronic products worldwide. The efforts by Si2s LPC coalition members are enabling the industry to implement low-power semiconductors that reduce costs and risks and development times.

The CPF standard reduces this risk by extending the industrys RTL-GDSII design infrastructure to support low power design techniques in a safe and efficient manner. In a little over a year the LPC has taken the next step to broaden the applicability to an even larger set of designs and methodologies with CPF 1.1.

CPF is a Tcl-based format used to capture the power intent of a design. CPF complements the RTL and/or netlist description of the design allowing existing golden RTL blocks to be used without modification. CPF has achieved wide acceptance in EDA tools in end-user tool flows, and enjoys a record of numerous completed chip tape-outs with subsequent testimonials, and adoption into leading foundry reference flows.

The extensions in CPF 1.1 further expand support for bottom-up and top-down hierarchical flows and enable the integration, reuse and verification of internal and 3rd party developed power aware IP. Power intent for multiple IP blocks from multiple sources can be integrated together with appropriate resolution of power domains, power modes and power related rules. In addition, CPF 1.1 supports sophisticated macro modeling of hard IP such as embedded memories with complex power structures. This enables implementation and verification of the IPs power behaviors in the design context.

CPF 1.1 expands the number of power domain operating states to include reversed biased and forward biased states. This enables the support of additional sophisticated power minimization techniques that are becoming more common in low power designs. CPF 1.1 improves the modeling of transitions between power modes which enables in-depth verification to ensure that the design can successfully enter and exit each operating mode, preventing a common source of failure in low power designs. CPF 1.1 also provides a new general model to describe power requirements for special low power cells such as state retention, isolation, always-on cells. This improves designer productivity by further automating implementation and verification of the design power intent.

Gill Watt, CAD Manager at AMD, and chair of the LPC said, "The LPC members recognize that the marketplace is demanding more power efficient designs for both mobile and wired products. CPF 1.1 contains major enhancements to extend its applicability to new design styles and methodologies. These enhancements provide greater flexibility particularly for designs that re-use IP from multiple sources. This flexibility is expected to expand the use of power-aware techniques from specialized power-critical designs into widespread practices used in all mainstream designs, allowing LPC member companies to provide more power efficient products to the marketplace."

CPF 1.1 is available for download at:


The CPF standard was approved and made publicly available in March of 2007. CPF is supported by many adoption aids and tools, all available from Si2: a CPF tutorial (in both English and Mandarin), a CPF Parser software, the CPF Pocket Guide, a LPC Glossary. A CPF Relational Analyzer is available to LPC members. CPF is supported not only by the Low Power Coalition, but also the Power Forward Initiative,

About the Low Power Coalition (LPC)

The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, ChipVision Design Systems, Entasys, Envis, Freescale Semiconductor, Global Unichip, IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Corporation (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL). The Low Power Coalition is an open industry group operating under the auspices of Si2. All interested parties are invited to join existing LPC members and participate. For further information on the Low Power Coalition, see

About Si2

Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents nearly 100 companies involved in all parts of the silicon supply chain throughout the world. Web site:


Silicon Integration Initiative
William Bayer, 512-342-2244, ext. 304 (office)