DVCon Expo, February 24-25, Doubletree Hotel, San Jose
SAN JOSE, CA--(MARKET WIRE)--Feb 17, 2009 --
Real Intent, Inc., the innovator in automating the intelligence of formal techniques for design verification, will demonstrate how they deliver verification confidence for ASIC and FPGA designs, at Accellera's Design and Verification Conference (DVCon) Expo, in San Jose, California.
Real Intent will feature its 2-for-1 Appreciation Promotion for new and existing users of its software, and demonstrate Ascent(TM) for automatic verification, and Meridian CDC(TM) and Meridian FPGA(TM) for Clock Domain Crossing (CDC) for ASIC and FPGA designs, respectively.
Tuesday, February 24 - 2:00-6:30pm - Bayshore Ballroom
Wednesday, February 25 - 1:00-6:30pm - Bayshore Ballroom
Booth # 403
Doubletree Hotel, San Jose, California
For more information about Real Intent, please visit www.realintent.com.
For information about DVCon, please visit www.dvcon.org.
About Real Intent
Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application specific integrated circuit (ASIC), system-on-chip (SoC) and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses around the world use Real Intent software.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web: www.realintent.com, e-mail: Email Contact.
Meridian CDC, Meridian FPGA and Ascent are trademarks of Real Intent, Inc.
All other trademarks and tradenames are the property of their respective owners.
Valley PR LLC for Real Intent