New Functionality Broadens UPF Parser/Analyzer Capabilities
ALAMEDA, CALIF. –– May 16, 2017 – Verific Design Automation, the recognized leader of SystemVerilog, VHDL and Unified Power Format (UPF) Parser Platforms in production and development use throughout the semiconductor industry, today announced availability of its UPF Elaborator.
The new functionality broadens the capabilities of Verific’s UPF Parser/Analyzer, available since 2014 and in production use within several chip design flows. It complies with the IEEE 1801-2015 standard (UPF 3.0) as well as previous versions 1.0, 2.0 and 2.1.
Lawrence Neukom, senior member of technical staff at Verific, is a co-author of the standard and a voting member of the IEEE 1801 UPF Working Group. “As engineering groups have found, UPF eases specification, simulation and verification of chip designs with power intent in mind. Our new UPF Elaborator extends our support for UPF by providing access to a power-aware netlist.”
The Verific UPF Parser/Analyzer reads a UPF specification command by command, maintaining line and file origination information, and executes syntax and semantic checks to ensure correctness of the UPF specification. The result is a resolved power-intent model.
The UPF Elaborator applies the power-intent model to the original hardware design language (HDL) design. The result is a power-aware netlist with new instantiations of power-related cells, as well as any required supply network and corresponding control path logic.
UPF concepts elaborated in an HDL design by Verific’s UPF Elaborator include logic and supply ports and nets, power switches, retention, isolation, level-shifter and repeater cells.
Verific’s SystemVerilog, VHDL and UPF parsers are in production and development flows throughout semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compiles on all 32 and 64 bit Unix, Linux, Mac and Windows operating systems.
Verific will exhibit at the Design Automation Conference (DAC) in Booth #639 June 19-21 from10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas. DAC attendees are invited to visit the Verific booth to learn more about the new Elaboration Module and its Parser Platforms and pick up this year’s giraffe giveaway. To schedule an appointment, contact Rick Carlson, Verific’s vice president of sales. He can be reached at (970) 948-9650 or via email at Email Contact. More information can be found on the Verific website.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effectively. Since 1999, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email:
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