LIVE WEBINAR: OSVVM and UVVM - VHDL Verification Methodology
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LIVE WEBINAR: OSVVM and UVVM - VHDL Verification Methodology

OSVVM and UVVM - VHDL Verification Methodology

Presenter: John Aynsley, Doulos CTO
Friday, May 11, 2018


Constrained Random Verification with UVM, the Universal Verification Methodology, is now firmly established as the workhorse for simulation-based verification, in the ASIC and SoC worlds at least. But UVM is built on top of SystemVerilog, which leaves you with a problem if you are a VHDL user looking to improve your verification. Should you stay with VHDL, or make the investment in skills and tools needed to move up to SystemVerilog and UVM?

In this webinar, we describe and explain OSVVM and UVVM, the Open Source VHDL Verification Methodology and the Universal VHDL Verification Methodology, which are free, open-source VHDL libraries. These methodologies allow VHDL users to start taking advantage of constrained random verification techniques without moving from their native VHDL language and simulator.

We also show examples of using dedicated features of  Aldec's Riviera-PRO™ simulator to display coverage information from OSVVM.

Doulos CTO, John Aynsley, will present this training webinar, which will consist of a one-hour session (see below for details) and will be interactive with Q&A participation from delegates. 

Attendance is free of charge.

Event Info                                                                 
EU and US Sessions

For Europe and Asia
10-11am (BST) 
 11am-12pm (CEST) 
2.30-3.30pm (IST)

For Americas
10-11am (PST)  11am-12pm (MST) 
12-1pm (CST) 
 1-2pm (EST)

 Friday, May 11, 2018
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Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.