Twenty fifth Annual IEEE Electronic Design Process Symposium
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Twenty fifth Annual IEEE Electronic Design Process Symposium

Twenty fifth Annual Electronic Design Process Symposium

September 13-14, 2018

Semi,  673 Milpitas Blvd, Milpitas, CA 95035

May 24, 2018 -- This year marks a milestone in the EDPS’s history as it turns 25.  We have come a long way since the early days of EDPS in Monterey.  In 1992, designs were beginning to truly explode rapidly moving into “very large scale integration” with companies racing to meet/beat the NTRS.  The words low-power and SoC design flows were but a whisper.  SIA was bringing out its first edition of National Technology Roadmap for Semiconductors, which subsequently transformed into ITRS, and now the Heterogeneous Integration Roadmap & International Roadmap for Devices & Systems. As these roadmaps project semiconductor industry evolution, EDPS strives to be the leading forum for advanced chip and systems development and CAD methodologies currently in practice within the industry.

As we approach the end of Moore’s law scaling, innovative packaging techniques are becoming increasingly important as package, board and other system components drive significant cost reduction. Innovative and smart manufacturing methodologies and flows are also becoming increasingly important. Since algorithmic development is changing rapidly, smart manufacturing enabling reduced NRE and faster time to market is critical.

Key changes in designs and design methodologies continue to be an EDPS focus; the leading industry members will be talking and sharing their challenges and solutions in this vibrant symposium. It’s the closest thing to real conversation about real design. EDPS 2018 sessions are based on the following themes


Please contact Shishpal Rawat ( Email Contact) to submit abstract and discuss areas of mutual interest.  All presentations slides must be made available in final form by Aug 15, 2018.

Complete presentations from 2017 EDPS and previous years are available at:

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