RISC-V Foundation Announces Agenda for RISC-V Workshop Zurich
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RISC-V Foundation Announces Agenda for RISC-V Workshop Zurich

The two-day Workshop will feature more than 40 presentations from RISC-V Foundation members

ZURICH — (BUSINESS WIRE) — April 30, 2019 — RISC-V Foundation:

WHERE: ETH Zurich, Gloriastrasse 35, CH 8092 Zurich, Switzerland

WHEN: Tuesday, June 11 to Thursday, June 13, 2019

WHAT: The RISC-V Workshop Zurich will showcase the open, expansive and international RISC-V ecosystem. The event will highlight current and prospective projects and implementations that influence the future evolution of the free and open RISC-V instruction set architecture (ISA), with a focus on the momentum and growth of the RISC-V Foundation across Europe and beyond.

The event will feature two full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. RISC-V Foundation members presenting at the Workshop include: AdaCore, CEA, CloudBEAR, Dover Microsystems, Draper Labs, Embecosm, ETH Zurich, Hex Five Security, Huawei, Microchip Technology, OneSpin Solutions, Princeton University, Qamcom Research & Technology, Rambus, SiFive, Syntacore and Western Digital. The third day of the event will feature meetings for RISC-V Foundation members.

Tuesday, June 11, 2019:

Wednesday, June 12, 2019:

To register for the event, please visit: https://tmt.knect365.com/risc-v-workshop-zurich/purchase/select-package. To learn more about sponsorship opportunities, please visit: https://tmt.knect365.com/risc-v-workshop-zurich/sponsor.

For press interested in attending, please email: risc-v@racepointglobal.com to receive your complimentary pass. To learn more about the RISC-V Foundation, its free and open architecture, and membership information, please visit: https://riscv.org.

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.


Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
Email: Email Contact