Cadence Provides Powerful Low-Risk SystemVerilog Verification from Plan to Closure; Incisive Design Team Product Family Overcomes Obstacles That Have Limited SystemVerilog Adoption
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Cadence Provides Powerful Low-Risk SystemVerilog Verification from Plan to Closure; Incisive Design Team Product Family Overcomes Obstacles That Have Limited SystemVerilog Adoption

SAN JOSE, Calif.—(BUSINESS WIRE)—Oct. 24, 2005— Cadence Design Systems, Inc.(NYSE: CDN) (Nasdaq: CDN) today announced the Incisive(R) Design Team family, tailored for RTL design teams looking for a low-risk, yet powerful way to adopt SystemVerilog-based verification from plan to closure. The product family leverages proven verification process automation (VPA) methodologies, technologies, and management solutions from Cadence's acquisition of Verisity. The Incisive Design Team family overcomes many of the obstacles that have until now limited SystemVerilog adoption. These include language maturity, verification IP interoperability, proven methodologies, and availability of supporting tools from assertion and test planning through formal analysis, simulation, acceleration and RTL closure.

Part of a new three-tiered Incisive platform, the Incisive Design Team family includes broad SystemVerilog language support, new product integrations, and tightly coupled methodologies optimized for design teams tasked with RTL verification. The family includes:

-- Incisive Design Team Manager, a new version of the Incisive Verification Manager for SystemVerilog and VHDL-based verification management, from assertion test planning and tracking, to failure and RTL coverage analysis.

-- Incisive Design Team Simulator, enhanced with new SystemVerilog testbench extensions, comprehensive SystemVerilog assertion (SVA) support, and integration with the Incisive Design Team Manager.

-- Incisive Design Team Xtreme Server, the easiest to adopt, simulator-like acceleration and emulation solution, with SystemVerilog DPI and SVA support in Q1'06, and integrated with the Incisive Design Team Manager.

-- Incisive Design Team Formal Verifier, optimized for design team use prior to testbench availability, with new SystemVerilog SVA extensions.

-- A packaged plan-to-closure methodology, tailored for RTL design teams adopting SystemVerilog for verification. The methodology offers incremental steps to improve productivity, quality and predictability with maximum impact and minimum risk. It also includes modules for dynamic and formal assertion-based verification (ABV), verification IP reuse, testbench automation, coverage, and verification management. Plan-to-closure leverages proven eRM and sVM methodologies from the Incisive Enterprise family.

"We're very glad to see Cadence going well beyond mere language support with a solution that couples leading simulation and testbench automation solutions," said Peter Hutton, vice president of Engineering at ARC International Inc. "The Incisive Design Team family delivers the technology we need with proven process automation methodology, based around the SystemVerilog language."

Aggressive SystemVerilog-based VPA Roadmap

This new family of Design Team solutions represents the first major step in Cadence's roadmap to offer world-class verification solutions based on SystemVerilog. As part of its "VPA Enablement" program for SystemVerilog, Cadence engineers will continue to work closely with customers on more advanced SystemVerilog capabilities. The program's goal is to infuse best-in-class technology and methodology from established products such as Specman(R) Elite and Incisive Verification Manager into SystemVerilog-based solutions.

"The SystemVerilog language has evolved faster than the tools and methodologies required to support it," said Moshe Gavrielov, executive vice president and general manager of the Cadence Verification Division. "The Incisive Design Team-family represents a major step forward by leveraging Cadence's extensive verification technology, management tools, and plan-to-closure methodology. The combined offering will allow Cadence to jump ahead with the highest-value SystemVerilog-based offering in the industry."

"Nethra is focused on meeting aggressive design schedules," said Clement Ip, vice president of ASIC Engineering at Nethra Imaging. "The more time we invest on design and verification up front, the faster we get to market through minimized design risk. Using the Incisive Design Team family from Cadence allows us to verify the design much earlier in the cycle, allowing us to hit our goals with a high level of confidence."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, Palladium, Incisive, Specman Elite, and Xtreme are registered trademarks of Cadence Design Systems in the United States and other countries. All other trademarks are the property of their respective owners.



Contact:
Cadence Design Systems, Inc.
Ric Chope, 650-934-6820

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