VMM-based verification components can now be seamlessly reused within an OVM environment. In addition, entire VMM environments can be reused without modification within an OVM environment through the use of a new OVM/VMM Interoperability library that provides the data and semantic conversions between the old and new environments. VMM sequential stimulus can be reused as well, and integrated with OVM’s sequences thus preserving and enhancing existing stimulus generation capabilities.
As an active member of the Accellera VIP Technical Subcommittee (TSC), Mentor has worked with other committee members to define the requirements for interoperability among different verification methodologies. Mentor’s solution conforms to the Accellera VIP-TSC’s set of requirements for SystemVerilog base class library interoperability that was approved by a technical subcommittee vote on December 3, 2008.
“Interoperability of verification IP (VIP) is critical to achieve productivity gains as design teams reuse legacy IP in an OVM environment,” said Stephen Bailey, Director of Marketing for the functional verification division at Mentor Graphics. “This solution provides an optimal means for VMM users to adopt the OVM with minimal effort. It also paves the way for the TSC to deliver an interoperability guideline document.”
“As a leading supplier of IP, Denali is pleased to see Mentor’s open-source solution as the first tangible effort at true VIP interoperability,” said David Lin, Vice President of Marketing, Denali Software Inc. “This solution presents advantages for us, as we continue to deliver best-in-class OVM-compliant VIP, and for our customers, as it broadens their choices and VIP access.”
The Mentor open-source SystemVerilog source code and documentation is distributed under the Apache2.0 open-source license, and is available immediately in the “Community Contributions” area of the OVM World site at http://www.ovmworld.org and at the Mentor Graphics functional verification website at www.mentor.com/go/cookbook.
About the Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million and employs approximately 4,450 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.