Structured ASICs ala eASIC
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Structured ASICs ala eASIC

Introduction

Structured ASICs lie somewhere between ASICs and FPGAs in terms of unit cost in volume, NRE, speed, area and so on. The situation is reminiscent of the fairy tale of Goldilocks and 3 bears where one bowl of porridge was too hot and one was too cold but the third bowl was just right. Is this the case for structured ASICs or does being somewhere in between mean not enough of some things and too much of other things?

Ronnie Vasistha joined eASIC as EVP of Marketing in January and in August took on the responsibilities of CEO from founder Zvi Or-Bach who remains president, chairman and chief technology officer. I had an opportunity to interview Ronnie recently.

Would you tell me a bit about your background?
Let me fast forward to what I do today and then go backwards. Today I am CEO of eASIC corporation. I joined eASIC in January 2005. I joined as executive vice president of marketing. That's what I do today.

I actually started my education in the UK in electronic engineering. I worked for a couple of companies in and around the UK for a while; a small chip company called STC, part of a large telephone cable company. Then I moved to Motorola primarily working in a wafer fab and test engineering. From there I moved to LSI Logic who had a wafer fab in the IUK at that time, a brand new wafer fab. I helped facilitate and build that fab plus helped put the process technology in. I worked in R&D in the process engineering world and in test engineering. I got to know the fab world, devices and yields very well. I then moved into some design and other areas in LSI Logic in an engineering capacity. About 10 years ago I made the move to marketing, product marketing in specifically. Not just designing and building chips now but actually defining what the technology should be and evangelizing that.

About 8 ½ years ago I moved to the US with LSI Logic. So I was with them for a total of about 17 years. I moved to the US where I was responsible for the definition of .18 micron technology or product, everything from what transistor to what the design environment should be. I left LSI as VP of Marketing in November of last year and joined here in January. Hopefully that gives you a little bit of color for my background.

What attracted you to eASIC, a much smaller company than LSI Logic?
I think primarily it was that I had been studying the space of custom logic design, working in it for maybe a year, trying to understand the challenges of standard cell design, of FPGAs and of everything in between. What really attracted me to eASIC is that I thought it had the exact right combination of two things that are very difficult to change. One is the technology underpinning any company. The second is the market timing of the requirement or need for that technology. Those two things are I think unique here at eASIC. It has exactly the right technology and the right market timing. Now the challenge is one of execution, of making that technology into products on a large scale. The attraction was really those two things; the right technology at the right time. As I've said I spent many years looking at things that are just now starting to become trendy, things like structured ASICs or platform ASICs etc, etc. That was my specialty.

What were the challenges you faced when you came on board in a marketing role?
The challenges were both company as well as market. The company obviously is a small company. There is a benefit to that in that you are very nimble and very quick. The down side is that you encounter a small company challenge from spending money to raising money, the traditional small company challenges. The challenge in terms of the product is taking what I think is fundamentally world-beating and building products that are really out of the box, shrink wrap by any particular user. One of the value propositions of eASIC is that we're enabling hardware customization for any user whether they be FPGA users or they be traditional high end standard cell design users. To enable us to do these things hundreds if not thousands of designs per year one needs to create a product that is very robust. That's really the big challenge that we were facing when I joined.

You joined eASIC as EVP of marketing and then became CEO. Did you come on board with the understanding that this would or might happen? Did something happen to cause this other than recognition of your talent?
I didn't come on board with that understanding. I came on board as head of marketing. But you're right. What really happened through the course of this time as any company goes through its natural progression, particularly a small company, you start to seed people into areas that they are able to deliver. You basically maximize the potential of the individual. I was given the opportunity by the board to grow into the area of CEO to maximize my potential as an individual. I think that you have hit the nail on the head. It was really recognition of some of my capabilities plus some of the background I've had and some of the capabilities of the original founder and CEO, a great technologist and to enable him to focus on development.

What challenges do you see in taking over the reins from a founder to remains as CTO and chairman?
It's been going actually very well. I'll give you the real insight; very rarely would anybody come into this situation knowing that there's going to be a huge challenge. One doesn't have enough time in one's life or career to face those challenges continuously. Zvi Or-Bach, who is that individual, and I had spent a lot of time together and we've spent a lot of time since. The reality is that we are both really focused on growing the company. Zvi relishes I think the opportunity to do some advanced development which he wasn't able to do. When the company was founded in 1999 the company was focused on patent development and technology. Since then we have not been able to do as much of that as we would have liked to because he has been faced with running the company. So I think the reality is that we both feel that this is better for the company. But there are always challenges. The good thing is that the two of us aren't the entire team. You've got the Board and the other key executives of the company, all extremely seasoned. Our Board, these guys have been around the block a few times and a few time more. Each one of us has a pretty strong say on the way the company should be run. Sometimes there's agreement, sometimes there's disagreement. Ultimately the executive team works well enough to carry the day.

Would you say something about the revenue, the size of the customer base, … ?
We actually started the company off as an IP business model in 1999. It was embedded IP into an ASIC. Our first customer was STMicroelectronics. ST is now shipping product. They announced a product called Spear only a few weeks ago around our technology; the first real release of our IP into the general market. Why I came on board was last year the company decided to release a family of standard products called FlexASIC around this technology. That standard product is just starting to ship now. We're going through the first customers' tape out of those products now. So we are really kind of in the early stages of revenue because we've moved from a pure IP company to more of a fabless chip company with still some IP. So really the first few years were one of developing, working with key partners such as STMicro, embedding the technology into their products. Now we've just started releasing our own array of standard products.

How many employees at eASIC?
We have about 90 employees.

Are these employees centrally located or spread around?
We have about 70 of them in Romania. The development has been carried out primarily in Romania with VP and lead managers located here.

Why Romania? Did the founder have some connections there?
There was a connection with a prior company. Our founder was also founder and CEO of ChipExpress. There was a Romanian connection there. He was able to continue some of those connections when he founded this new company. In addition to the 70 Romanians we've just opened a development office in Penang, Malaysia. We're in the process of hiring and recruiting for that office.

I'm assuming that the rationale for going to Romania and now Malaysia has to do with the cost of talent.
I'm sure you've reported on this aspect of our industry at length. What I would say is that it is a combination of factors. One is cost and the other is the experience that one can get and the ability to retain that. Retention has its good side and its down side. The good side is that you can keep employees productive as well as part of a team, a team that works well together. The downside is that you don't tend to get a lot of new experience into the company. So it's a combination of these factors as to why we have chosen these countries. In Romania you have a combination of raw math and engineering talent that we can retain. When you train them its easier to retain that team and keep them together as a working team. The downside is that you don't tend to get a lot of experience into the company; people with ten years. In Malaysia you tend to get people of that caliber as well. So a combination of factors - retention and the ability to hire experience people.

At a high level there are three markets out there, namely standard cell ASICs, structured ASICs and FPGAs. Could you characterize those three?
In general standard cell is a $20B market. The numbers vary slightly but the number of design starts vary between 1,500 and 2,500. It's relatively high revenue per design. Some of the very high revenue products like cell phones can swamp them but the general nature of that business is the cost of development and of development time has increased. The general nature is that you end up with high revenue per design requirement to start the design. The benefit of the design is that you can optimize that design for its end application and for its performance. That's the most optimized way of doing custom logic design which people outside of microprocessor do these days. At the other end of the spectrum is FPGAs. The number of design starts depending on whom you believe is closer to 80,000 or 100,000. The total revenue of that market is about $3B. You can see that this market is exemplified by very little revenue per design start. Some of those design starts don't actually result in any revenue. The reason for that is that it is the least optimum for the end application. You're starting off with a generic chip and you're trying to fit your design into that generic chip. So just by its nature it's a less optimized approach. They tend to consume large amounts of power, probably 400x the power of a standard cell. They tend to be much lower in performance, probably at least one fourth the performance of a standard cell. They tend to be a lot larger. The largest chips tend to be 2cm. They tend to be very costly. The benefit of them is that they are off the shelf components that you can match with the design environment and you can pretty much implement your design relatively quickly. It's getting more complicated as technology moves forward. Once you've done that design, if something is wrong you can remap your architecture or functionality again and again. So they are a verification vehicle and that's what they tend to get used for; prototyping and verification vehicles. Whereas a standard cell tends to get used as a production vehicle.

What has happened over the course of the last two or three years is that the gap between the two has widened. Some people would say that the gap has closed but it has actually widened because the capability of the standard cell has increased so much. But the cost of designing in advanced technology has also increased.

Along comes structured ASICs or platform ASICs, that's the product that you make some tradeoffs with. You may not get the most optimum implementation - die size, power and performance - but you can meet your needs. You don't get the absolute ability to reverify your functionality that you would get with an FPGA but what you do get is a faster turnaround time in design and manufacture. So you are making some tradeoffs. Most people are able to live with those tradeoffs, meaning design time becomes shortened and more predictable, the die size isn't much larger and in fact you can ship up to certain numbers of units in volume and feel very comfortable in doing so from a market penetration perspective. What happens now is that people are able to start over again designing in hardware customization. Before they had started to stop doing that. That's where structured ASICS fit in.

Why did I join eASIC? I believe that they have a unique and compelling proposition within that structured ASIC approach and also embedded IP within the standard cell approach. You really hopefully start to reverse the trend of standard cell design starts declining and actually increase them by embedding our technology in there and allowing all the customization of the chip. We are basically building customizable platforms as opposed to real ASICs.

If structure ASICs is a compromise between two extremes, is there a risk that no one would be satisfied? Is there a major market for this?
There is definite a major market for this. You're not wrong when you said that. The challenge is making sure that the tradeoffs one is making and the approach you're taking to this market are beneficial to the customer. There's definitely a large market for this type of product but you don't want to create a product for this market that is say half the cost of an FPGA. You want to create a cost differential that's markedly compared to the unit price of an FPGA. At the same time you've got to make the design faster and significantly less costly than the standard cell design. You've got a few parameters, a few knobs to twiddle and turn till you get the right wining solution. I think the experience in this market has shown, I've worked a lot in the standard cell world and spent a significant time looking at he FPGA world. I think we know where those knobs, those dials that need to be set for it to be meaningful Underpinning that as an example eASIC has a one via stage customizable approach which essentially means no masks are need to be made, there's no upfront NRE. STMirco was able to show with our technology that they were able to get RTL to GDS II in 24 hours. We are cutting the cost of design as well as significantly cutting the NRE costs. The chip price is not significantly different in volume from that you would get from a standard cell because our density ranges from half a standard cell to actually 2X density in one benchmarking. Turning these knobs exactly right is very important.

How do you deliver your product? Do you have wafers stored somewhere?
The final product is delivered as chips to the customer. We're a fables company so we deliver chips at the end of the day. The product enables them to get to that point is the design environment that we provide. We have a partner we are working with, Magma, who provides tools that support our design environment. Then we provide the libraries. We work with third party IP providers as offer our own IP to the customer.

Any plans to work with Cadence, Synopsys or Mentor Graphics?
We use some of their tools internally. We actually have a design flow if a customer wants to utilize a Synopsys or Synplicity tool for synthesis. That's where we are today. Magma is our strategic partner. A customer can use Synopsys logical synthesis as well. We haven't got any plans at this moment with eh other vendors.

Are there any other vendors in this space that you see as competitors?
I think the main competitors are some of the existing ways of doing things; FPGA for instance or very low end standard cells. The other structured ASICs or platform ASICs are really more of a variation on a theme from some of those existing approaches. Some of the other people in structured ASICs are NEC, LSI Logic - I know them very well. Those kinds of people are really more of a variation on existing ways of doing things as opposed to a kind of dramatic difference. I see eASIC technology as being very disruptive. That's why I came here. I don't see anybody else with this kind of disruptive approach.

Disruptive approaches usually a lot of missionary selling. What challenges to you face to convince people that your products deliver?
That's a very good question. One of the things I learned is that disruptive can be good and bad. The way we've done that is to basically provide a very similar design environment. The customer from a user's perspective doesn't see much difference from what they're already doing. RTL is at the top. They go through their verification, they map or synthesize to our libraries using the Magma tools, BlastCreate. So they are very used to this kind of approach. The only difference is the output. They get a GDSII file which is essentially a via file. That's all they need to provide. Then there's the bit stream to program the logic. Really, it's just the output that looks slightly different. Everything else as far as they are concerned is exactly the way they've done things in the past.

The difference in the fab is that the wafers sit waiting for customization at a late stage. When the via file arrives at the fab, then the wafers are finished. The customer doesn't have to do or see anything different. They get the chips back, test them the way they do things normally and set those chips into their systems. From the user perspective it's not really a new experience.

How do you package and price your product?
We have two lines of business, the embedded IP which is more of a strategic relationship where we work with larger IDMs and larger ASSP companies. The packaging of that is more strategic together with services that we provide to their design team. The chip product comes essentially packages as an ASIC product which is a design environment together with P. They can utilize third party IP but it is one product that they get. One variation of that is that there are some options available to them on the backend like test vector generation and different test environments; standard for any chip company.

Pricing?
It's price per chip. How many are they going to buy and the complexity of the chip they are buying. We have a set of standard arrays. Prior to our engagement with the customer we quote them on their business. That' the price they pay per chip. No NRE associated with the design. They may take up some of the options at the back end.

What is eASIC's sales model, direct, indirect, ..?
Very limited direct. Mostly through what we call DSRs, design service reps. They're essentially people who are able to do this work, third party design houses. There are also some reps aligned to those organizations. We may engage with some reps ourselves. Very limited direct sales. I don't see us engaging any more direct sales going forward because remember our value proposition is to enable hundreds if not thousands of designs a year. We couldn't employ enough salespersons for that to happen. We have to enable and engage a channel.

What do you see as the challenges to recruit, motivate and support that channel?
The challenges are always one of making sure that they have product, product knowledge and understand enough about the product so that they can do it themselves. We are making something complex which is custom logic design very simple, so all of these service reps see the simple design side. The other challenge is the ability to provide to them the new technology as it comes along. Really a training type of element. Most of them have done custom logic. We just need to engage the ones that can provide the service that we require to our customers because at the end of the day that reflects upon us. The challenge is finding the right quality of rep. There are a lot of very small firms, 2 or 3 people, with design capability out there. When they see that they can do many designs per years with our product, they want to latch onto it. Some of those teams are very good. The challenge on us is to understand what their capabilities really are. We want them to be around for some time, not a short term partnership.

In terms of potential business and ability to recruit reps, do you see any differences in terms of geography?
We found that it is very hot in Japan. Don't quite know why. I think that's the same for a lot of startup, particularly in the space of doing something different. Japan thinks very quickly. Also we have a lot of traffic from people registering on our website. That's another sales mode we will have. They will be able to get all they require from our website. We are getting a lot of traffic from Asia: Japan, China and India. Anybody wanting to do custom logic designs can come onto our website and register. A very strong worldwide footprint already,

Any direct presence in Asia?
In Japan we have a sales office. We're just in the process of bringing someone on board to cover Asia as well.

When you became CEO there was no publicity which usually occurs. In fact your website now features an article from EE Times entitled “Vasishta quietly named CEO of eASIC”. Any reason for the low keyed approach?
There's a couple of things. You've kind of hit the nail on the head. This is sort of a standard thing that companies go through out there. It was a kind of standard thing with the founder and CEO moving into a CTO role. The other thing is that we saw the move of Zvi Or-Bach and myself as very natural for the company. Obviously we talked with a lot of people about it including EE Times. It was a very natural progression for us as a company. I think that there's some to be quite honest with you the fact that did you want to make a very big issue that the founder was moving into an CTO role? You can try to write a press release around that there is a new CEO now at the end of the day. We didn't see it as something that warranted a press release at the time. It was kind of a Board decision. You could do it one way or another. It wouldn't have made a lot of difference to any body on the executive team.

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