I won't say this is a sleek, efficient, or optimized pre-conference presentation on DAC, but I will say that if you read it top to bottom, you'll have a scatter-shot impression of what some (but not all) of your opportunities will be from July 23rd through July 28th in and around Moscone Center - and what you should be thinking about while you're partaking of those opportunities. Enjoy!
Rajeev Madhavan, Chairman & CEO at Magma Design Automation - [I spoke with Rajeev by phone on July 7th. I was in Silicon Valley; he was visiting family in Southern India, having just come from meetings in Japan, Taiwan, and China.]
This year at DAC, we are basically the technology leader and will have a whole bunch of announcements and demonstrations going on at 65 nanometers, and even 45 nanometers. Unlike other EDA companies who buy their technology, ours is home grown. Typically, EDA companies grow through acquisition, but Magma likes to buy companies either very early in development or develop the technology ourselves.
There is a growing EDA industry in India. I have just come from a week in Bangalore and Hyderabad, where I met with many EDA and IP start-ups. They were looking for help and advice from me, and I found at least a couple of them doing innovative tools. Actually, I've never seen EDA start-ups in India before. I've seen IP start-ups in the analog [area], but never EDA start-ups. These companies are trying to write their own tools, but they are [somewhat] poor at business. They need expertise in raising money, and moving from mom-and-pop shops to [larger enterprises]. There are some big mistakes being made, so many are bound to fail. But, by the next generation of companies, there may be some that succeed who will add quite a bit of value [to the EDA industry] here. It will take time, but it will happen.
There is a huge amount of design being done here in India. Many global companies are here - Texas Instruments, Infineon, and many other customers. There is also a [growing] ability to write software tailored to these companies. And, cutting-edge designs are being done here, 65-nanometer designs. It's definitely happening - you have very complex chips being done here now. The design teams are fighting to do [more and more] of the cutting-edge designs.
So, with those design skills here and the software skills here, innovation in EDA is bound to happen here as well, because there's tremendous drive to do it. We see it in our own R&D team here in India. Several patentable inventions have happened here, and there are bright, young kids here with energy being managed by our team in Santa Clara. Now, we need to build more managers here in India. [That will happen] over the next 2 years or so. We need to be able to manage our growing talent pool here.
Magma is truly an international company, and yes we do also have an office in Beijing. We have 13 or 14 people there writing code, and experimenting in one or two areas. However, as with [all international companies], English is the lingua franca - which works in India. In China, however, I still need an interpreter. English is still not widely spoken and we have some difficulty managing our team in China from Santa Clara. Clearly, English is an advantage [that India has over China].
The other problem is that no one is really doing 65 or even 90-nanometer designs in China. At Magma, we 'go in the door' of our customers when they are doing cutting-edge designs. But when you're doing older geometries, you're using older tools. There is one other difference in China. In India, most of our customers are U.S. or European-based companies with operations there. In China, the customers are companies that are [state-owned]. I hope the Chinese government will relax a bit [going forward], to allow for a more free economy, but it's difficult to do that in that environment. So, we see our business continuing to increase in India because of the multinationals, [more so] than in China for now.
It does require a lot of travel on the part of management, but [we are growing] our local management and our local talent pool in these areas - people who know how to write and support EDA software. And yes, absolutely - human interaction across the teams [and geographies] is required! But that's one thing we have always done well, to [promote interaction] across teams. On a quarterly basis, we fly 80-to-90 percent of the company into Santa Clara to make sure that everyone gets it when change in happening. [Similarly, of course], DAC definitely helps Magma. It's a good opportunities for us to bring our users together. We organize ourselves at DAC to do that, and we do it well.
Accellera Technical Excellence Award - The standards body has named verification expert Harry Foster as the 2006 recipient of the organization's 3rd annual Technical Excellence Award for his contributions to Accellera's Open Verification Library (OVL) standard. The award will be presented at Accellera's Open meeting at DAC on Wednesday, July 26th, at 10 AM in the Marriott Hotel's Golden Gate Room B2. You should go, if you know and admire Harry (and who doesn't?), and/or you know that the OVL library standard includes assertion checkers used by design, integration, and verification engineers to check design behavior with simulation, emulation and formal verification tools. Harry Foster is the inventor of OVL and was a driving force behind the movement to make it a standard, where it has brought about fundamental changes in the verification industry, and the move towards Assertion-Based Verification (ABV). Harry is principle engineer for the Mentor Graphics Design, Verification, and Test division, and serves as chair of the IEEE 1850 Property Specification Language (PSL) working group.
Adam Traidman, President at Chip Estimate - We have formed a foundry partner program. Chartered Semiconductor Manufacturing is the first foundry to join. Chartered customers will now be able to go to www.ChipEstimate.com and search for IP from Chartered IP partners, as well as through a link from Chartered’s website. These IP partners have developed IP spanning several generations of Chartered’s technologies, including advanced technologies using 90-nanometer and 65-nanometer processes. At ChipEstimate.com, design teams can view a list of Chartered IP partners, view those partners’ IP datasheets, and review IP status in silicon. By leveraging our IP search capabilities, Chartered’s customers can easily locate the comprehensive IP options available to them.
ARM & Mentor Lunchtime Panel - It's Thursday, July 27th, from 11:30 AM to 1:30 PM and it's called, "Efficient Multi-vendor Design and Verification flows - Proof that they exist!" The idea under discussion is that traditional design, development, and verification methodologies have difficulty supporting the complex task of creating and verifying multi-processor embedded designs. Therefore, this ARM and Mentor seminar will look at an advanced system optimization and verification solution, which addresses an automated flow - from SystemC platform development, through to fabric generation and full-system assembly including complex configurable IP, to software creation and full-system verification. It's all about creating a true multi-vendor design chain, and doing lunch at the same time. It's about multi-tasking! Oh, and by the way - this ARM/Mentor flow integration uses IP and tools conforming to The SPIRIT Consortium's XML specifications.
Book Signing - On Monday, June 24th, at 4:15 PM, Lee Wood of MP Associates is hosting a "mass" book signing in the DAC Pavilion on the Exhibit Hall floor. I suspect there will be many authors present, but the book that I hope will be there is The Electronic Design Automation for Integrated Circuits Handbook. This massive, 2-volume work edited by Louis Scheffer, Luciano Lavagno, and Grant Martin is a rich resource for anyone who really wants to delve into the details of what makes the EDA industry tick. The list of luminaries that have composed the 45+ chapters in the set reads like the proverbial Who's Who of EDA. I'm not going to list any names, because they should all be listed, but suffice it to say - Grant Martin sent me a copy of this boxed set and I have spent a number of hours turning pages and enjoying the technical depth and breadth it offers, and marveling at the list of contributors. The text is extremely well written, and each chapter includes a lengthy list of references - the chapter on Logic Synthesis alone includes 249 papers and sources. I'm not suggesting that everything you ever needed to know about EDA is in this boxed set, but if you want a launch point to begin a thorough study of a topic, or a topic within a topic, related to electronic design automation, I don't think, today, you could find a better place to start!
Cable Cars - At 5 bucks per ride, they're way too expensive. But if you've never ridden one What, you can't part with 5 bucks? Just do it! You won't find any locals on board, but who cares?
Castro Theater - Lovingly restored, complete with organ that rises up from below, and an eclectic set of films most days of the year it's part of the San Francisco scene.
CEDA Distinguished Speaker Reception - The lecture by Mentor's Janusz Rajski and reception will be on Monday, July 24th, from 5:30 PM to 7:30 PM in Room 124 at Moscone Center. This event is part of a series sponsored by CEDA to honor the best papers at DAC, ICCAD, and TCAD. Rajski et al's paper was the TCAD 2006 Donald O. Pederson Best Paper, co-authored with J. Tyszer, M. Kassab, and N. Mukherjee, and titled, "Embedded Deterministic Test."
City Hall, Opera House, Davies Symphony complex - All Blue & Gold, the City Hall is a benediction to the other two structures. The whole thing is best enjoyed from the second floor lobby of Davies Hall. Go and you'll see why.
Cliff House - It used to be beautiful, several iterations ago. Now it's just a hunk of cement. But the view is most spectacular. If you're a tourist, you'll love the food. Otherwise, eat elsewhere.
Coit Tower - Don't even ask why you need to go. Just go. The view? Yes! The WPA murals in the lobby of the building? Historic and terribly moving.
Convergence at DAC - According to a spokesperson at STMicroelectronics, Alessandro Cremonesi's keynote address, on DAC Thursday will help attendees answer the question of whether convergence is a technical reality or a business strategy. Cremonesi is ST's Strategy and System Technology Group Vice President and Advance System Technology General Manager, and he is promising to highlight a number of existing and possible future applications in his talk, to identify various challenges in designing convergence applications for today and tomorrow, and to discuss the business opportunities - and threats - that both entrepreneurs and entrenched players should be aware of. He will also testify to the fact that the design community, with substantial help from its friends in EDA, has made lots of progress merging, and converging, technologies to improve contemporary life - but there's still lots of work to be done, on both the technical and business sides. The intention of Cremonesi's keynote address is to let attendees know what they can do to contribute to those efforts. The event takes place in the Gateway Ballroom at 12:45 PM on Thursday, July 27th. Be there!
Darren Tay, CEO at Nanno SOLUTIONS - Nanno SOLUTIONS' technology makes use of a fab's actual process variation data and transforms it into realistic values, which enable designers to improve design performance, including parametric yield. The first products, Nanno-WiN and Nanno-CaL provide realistic, statistically based, worst-case interconnect models for RC-delay, crosstalk and IR-drop. Nanno SOLUTIONS' models can be used for front-end, as well as back-end design during the pre-layout stage. They are built using actual process data from the fabs to improve accuracy, run-time, accelerate yield prediction and reduce design skew.
Dennis Brophy, Mentor Graphics - The must-see, must-attend verification lunch on Tuesday is with "the" MythBusters as Mentor details its AVM 2.0 Cookbook.. First-come, first-serve seats are available, but going real fast! Added bonus: the first fifty to visit the Denali booth after lunch, get Denali party tickets for that night. It's all happening Tuesday, July 25th, from 12:00 Noon to 1:30 PM in Room 102 at Moscone Center. With all these vendors at DAC telling you that their products are the best, how can you know what's true and what's hype? This sounds like a job for MythBusters! Come and meet the MythBusters from the Discovery Channel TV series. Special effects experts Adam Savage and Jamie Hyneman will show you how they use modern-day science to show you what's real and what's fiction by taking you inside the world of MythBusters. They will share their methodology for analyzing a myth and planning and constructing experiments to determine whether the myth is plausible, confirmed, or busted. The one thing they can't always do is correctly predict the outcome of their experiments. Sometimes, the bigger the myth the more spectacularly the experiment fails...or succeeds. Of course, when designing a chip, failure is not an option. At Mentor, we've created the Advanced Verification Methodology (AVM) to help verify the most complex designs. In the spirit of the MythBusters, whether you're a verification novice, or an expert like Adam and Jamie, you'll be able to use the AVM, building on the library Mentor provides, and reusing components across teams and across projects, to assemble the verification environment you need to confirm that your chip will achieve first-pass success.
Dennis George, Director of Marketing at Nascentric - It has been a significant year of growth for Nascentric since DAC 2005. Nascentric has engaged with several high-profile semiconductor manufacturers and IP vendors, added multiple partners (Cadence, Novas, ARM, Virage Logic, and Sandwork) and received two patent awards for its core technologies (Razor and Blade). To avoid marketplace confusion and potential legal action taken against us, Nascentric is also changing the name of its Fast-Spice simulator. At DAC this year, Nascentric will unveil the new product name as well as discuss the product's use across multiple markets and within multiple design flows.
DeYoung Museum - Clad in copper and surrounded by palm trees and the park, it's new, glorious, and an architectural gem. The building is as much an art piece as the content it houses. Go up to the top of the tower. You will not be sorry.
DFM Panels - “DFM: Where's the Proof of Value?” As mentioned in "The Business of DFM" in EDA Weekly on July 3rd, the moderator is Joe Brandenburg, and the panelists include Jacob Jacobsson, Atul Sharan, Joe Sawicki, Naeem Zafar, and Synopsys' Raul Camposano. This promises to be a fascinating hour and an appropriate end-point for DAC 2006. You should plan to attend. It's happening at 4:30 PM on Thursday, July 27th.
More on DFM - For more on DFM, please scroll down to the Addendum on DFM, where Prashant Maniar, Chief Strategy Officer at Stratosphere Solutions, chimes in on the questions posed in the July 3rd issue of EDA Weekly.
Prof. Diana Marculescu, ECE Department at Carnegie Mellon University - At DAC, we will be celebrating the 35th anniversary of the SIGDA Newsletter. Now distributed electronically, the Newsletter includes EDA News, upcoming events and funding opportunities and the new "What is...?" column on various EDA topics. Look for the ACM/SIGDA flyer in your DAC attendee bag where you will find excerpts from the first issue of this new column, along with Newsletter samples from the past. Also featured are the SIGDA Ph.D. Forum (see below) and the SIGDA/DAC University Booth. In the flyer you will also find a SIGDA/DAC trivia contest. Winners will receive a FREE SIGDA MEMBERSHIP for 2007 which comes with reduced registration rates at SIGDA-sponsored events, SIGDA travel grants, yearly EDA conference Supercompendium DVD, and the SIGDA Newsletter in your mailbox every two weeks.
EDAC Numbers - Don't look now, but the EDA 2006 Q1 numbers were virtually sizzling. A 10-percent revenue growth, per EDAC's Market Statistics Service poll. If that's not reason enough to come to DAC, I don't what is! And don't forget - EDAC sponsors the Gartner Dataquest Executive Briefing on Sunday, July 23rd, 5:00 PM, at DAC. Let me be candid about this must-attend event - it's a must-attend event. Savvy?
Erach Desai, Senior Vice President, Technology Research at Moors & Cabot Technology Research - There are only three things that should be on the average DAC attendees mind; be they a vendor, a tire-kicking customer, in PR, or just an astute observer: 1) I'm calling this “The DAC that Joe's Back!” Question is: is he really, really back, or just teasing us. Undoubtedly, his keynote will remind us of the leadership and vision that we have sorely missed for nearly 10 years! 2) Is DFM really an adjective, or an actual market segment? With 30+ start-ups looking for B+ round financing, it is kind of reminiscent of the 802.11/WiFi start-up days. Hmmm! 3) When is the tipping point for ESL? It's been all about the “back end” since Verilog and Design Compiler (circa 1990) revolutionized the “front end”. Now I'm not buying into the $1.6 billion ESL market pipe dream for 2009, but system-level design & validation tools should be approaching a $0.5 billion mark by 2010. Finally, my one big gripe is: who scheduled DAC during the peak week in quarterly earnings season? There was some justification about co-locating with SemiCon West, but that was winding down last week. Yikes!
ESL at DAC - Depending on what part of the 'political' spectrum you position yourself in, you may be thinking that someday it won't be ESL at DAC. It will be ESL is DAC. Happily, or unhappily, depending on your point of view, we're not there yet. Nonetheless, there are a plethora of offerings on the topic, populating practically every page of the DAC program this year. I would make special mention of the ESL tutorial, taking place on Monday, July 24th, from 9:00 AM to 5:00 PM. The emphasis will be on SystemC, but no matter how you come down on the topic of that particular language, you and I both know larger system-level design issues will be addressed. Speakers include: University of Tuebingen's Wolfgang Rosenstiel, ESLX's Jack Donovan, Philips' Maurizio Vitale, ST's Laurent Maillet-Contoz, Forte's Mike Meredith, and Summit's Vincent Viteau. And, don't go because you already consider yourself an expert on the topic - or a disciple of the language. Go because you're not yet an expert and you haven't decided where you stand on the language. Branch out! Stretch your mind! Jettison the chicken suit!
The Denali Party - Denali says it is pleased to announce that "Denali Live at the Fillmore" will open with the Full Disclosure Blues band featuring Gary Smith, Aart de Geus, and their gang of EDA industry veterans including Don MacMillen, Joanne Wegener, Takashi Yoshimori, Kevin Steptoe, Bob Gardner, Dave Neilson, and Grant Pierce. [Editor's Query: Gary, of all people, knows how to spell Z-y-d-e-c-o. Why isn't there an accordion in the band?]. After the not-Zydeco Full Disclosure set, Jim Hogan and the 3rd Street Coalition band will follow, with a special guest appearance from Cadence CTO Ted Vucurevich. Hopefully, Ted won't still be busy chatting about his work on the "Ask the CTO" panel, because all work and no play can really make someone dull - even Ted! After Full Disclosure and 3rd Street have exhausted their respective repertoires, Disco Inferno will take over for the bulk of the evening, for what is said to be their 7th straight appearance at this now larger-than-life event. Oh my - Denali is proud to report: This is the hottest ticket at DAC, but there is a limit to how many people we can pack into the Fillmore - so register today and reserve your ticket to Denali Live at the Fillmore. What Denali isn't saying is that the ghost of Bill Graham will be welcoming you at the door.
Fabless Model at DAC - Like San Francisco's favorite adopted son, reports of the death of the fabless model may have been greatly exaggerated. If you know what I'm talking about, then you've got an opinion on the subject - everybody does. If you don't know what I'm talking about, you need to attend the DAC Pavilion Panel on Tuesday, July 25th, from 4:00 PM to 4:45 PM. Canaccord Adams' Dennis Wassung is moderating, and Chartered's Walter Ng, Qualcomm's Matt Nowak, and SIGMA-C's Thomas Blaesi will be the panelists. [Editor's note: Who is San Francisco's favorite adopted son? Don't bother to come to DAC until you've figured it out!]
Fairmont Hotel - The legendary Julia Morgan supervised the redesign and resurrection of the building after the 1906 Earthquake & Fire. From there, she went on to spend 30 years designing Hearst Castle for William Randolph Hearst. You won't know San Francisco unless you at least step in. The vintage photos are along the north corridor leading to the glass elevator that no longer operates.
The Ferry Building - Beautifully restored as part of the Embarcadero post-1989 renewal, not only should you visit, you should plan on taking a ferry to somewhere across the Bay.
Golden Gate Bridge - Start at the North end and walk across to the South end. Turn around and walk back. Wear a jacket and enjoy the view. Choose a day when there's no fog.
Hugh Durdan, Vice President of Marketing at eSilicon - While the tendency at DAC will be to focus on specific design problems and tool solutions, the real buzz will be: "How do we get this done?" Designers want options to make their lives easier; sometimes this means new tools, but that's just the beginning. Outsourcing, IP acquisition, supply chain management - these are a few things that will be discussed at the design team collaboration panel, which will look at organizational issues beyond tool usage. New tools get headlines, but headlines don't get products out the door! This year, look for practical solutions to big picture challenges facing companies today. The panel, "Design Team Collaboration: Tools Challenge or Organization Responsibility," is happening on Tuesday, July 25th, from 11:30 AM to 12:15 PM and includes firstRain's Penny Herscher, DE Shaw's Marty Deneroff, eSilicon's Prasad Subramanian, and Matsushita's Taguchi Hirofumi.
Joe Sawicki, Vice President and General Manager for Mentor Graphics' Design-to-Silicon Division - Mentor will be showcasing its new nmDRC, part of the Calibre nm Platform, which fully redefines the traditional physical verification process. The system provides real-time debug, incremental verification, and significantly increased performance to allow designers to reduce overall cycle time and address the increasingly complex sign-off process of nanometer designs.
Joe Costello's Keynote - It's at 2:00 PM on Monday, July 24th, on the main stage at Moscone Center. Take pity on other events happening at the same time, because I suspect Costello will be the main draw of the hour. Currently he's chairman of Orb Networks, but it's his legacy in the EDA industry that caused him to be invited to give this address.
John Cooley's Cheesy What to see at DAC - Rumor has it that you've got 'til end-of-day on Tuesday, July 18th, to send your special tid-bits to ESNUG's John Cooley if you want to be mentioned in the honor roll of contributors to his Cheesy Best of DAC column, which I believe is going to posted on July 19th or 20th. (I think that's the title of Cooley's upcoming pre-conference prose poem on the Design Automation Conference, but I could be wrong so don't quote me on that.) If you don't know how to reach Cooley, go to deepchip.com and search around 'til you figure it out.
John Fleming, Senior Vice President and General Manager for Electronics at ENOVIA MatrixOne - I think the buzz this year at DAC will be around the increased responsibilities being thrust upon IC designers. The boundaries around their job descriptions are already being removed, meaning that in order to be successful in today's environment where semiconductor development is becoming more integrated with other parts of product development, they'll need to be more in tune with the company's entire design, development and manufacturing process - and learn to look at the larger picture.
Jon Atwood, Chief Logician at The LogicWorks - Jon sent this description of his compelling new adventure, On Demand Radio The electronic design community needs an independent forum and a voice. On Design Radio is a new podcast created to provide a platform for open discussion about the issues that face the design community as a whole. Today, more than ever, open communication is needed to bring together the separate constituencies that make up the design community. It's no longer viable to communicate just within the boundaries of each group. EDA, design services, foundries, IP providers, and VCs need a forum to come together to share ideas and build the design community of the future. On Design Radio strives to be the voice for this forum. [Editor's Note: If you haven't yet tuned into Jon's online radio show, give it a listen!]
Kamal Aggarwal, Vice President of Marketing and Strategy at SoftJin Technologies - Growing system and silicon complexity are the two key challenges being faced by IC designers, which shall be highlighted at DAC. In order to address the silicon complexity, IC designers and mask makers need post-layout tools that are customized for their needs. At DAC, SoftJin shall be demonstrating an enhanced version of its Nirmaan tookit for developing customized post layout and DFM tools. To address the system complexity, a number of innovative programmable platforms are emerging. At DAC, SoftJin will be demonstrating its Programmable Synthesis Engine that is customizable for specific architectures, thus enabling vendors to offer optimized and affordable synthesis solutions.
Legion of Honor - The single most beautiful location in The City, don't miss it. The views out to the Golden Gate Bridge, across the fairways of Lincoln Park, are legendary. The museum itself is lovely, as well. In a nod to Paris - the French paid for the museum after The Great War - the front patio comes complete with a petite glass pyramid.
Management Day - The business of technology is just as important as the engineering of technology. There's a plethora of presentations, sessions, and panels happening all day Tuesday, July 25th, that address the business side of the high-tech equation. Check it all out in the DAC schedule and plan to attend some or all of the offerings there.
Mark Hopkins - The lobby is small, The Top of the Mark is not. Every GI who passed through San Francisco between 1941 and 1945 was there at one point or another. Go and find out why.
Modesto Casas, President of In Region Inc. - This year's buzz will be the same buzz as last year's, and to some extent the year before. Got ESL? I believe that some EDA vendors are beginning to partition the problem, create solutions, and define what ESL means in terms of value to customers. That should make a buzz. Otherwise, you'll need a Platitudes@DAC section in your post-DAC newsletter.
Nanotubes, Nanowires, Nanochips, and Bio anything - Do you want to hear about the future? Go look at the DAC schedule. Pinpoint anything that starts with "nano." Go there. Bring the DAC Proceedings with you. You may need to be following the script as the play unfolds.
SF MOMA - The Museum of Modern Art is right across the street from Moscone. You have zero excuses for not carving out some time to go see it.
OVL at DAC - The OVL Technical Committee Meeting will have an open meeting on Wednesday, July 26th, from 1:30 PM to 3:30 PM, at the Marriott Hotel, Golden Gate Room B2.
Paul Rowbottom, Director of Technical Marketing at Advantest Technology Solutions - Advantest will demonstrate its new CertiMAX product. CertiMAX enables "real world" event-based semiconductor validation using a PXI-based environment without imposing any of the traditional limitations of cycle-based test. It revolutionizes the validation environment by allowing the functional verification, debug, and characterization of first silicon without deviating from the design environment. Chip designers can literally take an industry- standard VCD file from a simulation tool and use it as is, on silicon. By allowing the design data to be used directly without requiring vector, timing, or format translation, CertiMAX greatly simplifies the validation process DRAMATICALLY speeding time to market.
The Presidio - For this you need a car, but it's well worth the cost. Drive the whole park-like expanse. It's no longer home to the 6th Army. Instead, it's now home to, among others, George Lucas' new Industrial Magic & Light campus, which is just a gem.
Red's Java House - It's funky and just the excuse you need to walk along the newly resurrected Embarcadero, salvaged from concrete-clad obscurity after the '89 Loma Prieta Earthquake. From Willy Mays Plaza to the Embarcadero Center, it's the single most glamorous urban renewal project in the world. Put on your walking shoes and find out why. You'll know you're in the right location if you come upon the bow and arrow.
Rich Faris, Vice President of Marketing and Business Development at Real Intent - This year, Real Intent will be formally unveiling our new family of formal tools, the EnVision family. Conquest and Ascent, our new formal ABV (assertion-based verification) tools, are joined by existing products, Clock Intent Verification and PureTime, to complete the family. The promise of formal verification is that the time to quality is reduced, and tough bugs that can slip through using a dynamic approach are caught. Significant improvements in EnVision include patented automatic proof construction, a new assertion visualization capability, and a unique guided iterative process. To learn what the "Assertion Density Paradox" is, please come by see us at DAC.
R.I.P. - There are a number of companies that won't be with us this year, including ReShape, TransEDA, and Ignios. Such news begs the question: Better to have innovated and folded, than never to have innovated at all?
Scott Sandler, President and CEO at Novas Software - I think the 'buzz' at DAC will again be ESL and DFM. In ESL, it's "What is it, who will use it, and what will it do for EDA revenue?" While in DFM, it's “Which of the myriad players has real stuff that users can get value from?"
SIGDA PhD Forum - This is always a lot of fun, and it's happening on Tuesday, July 27th, from 6:30 PM to 8:00 PM in Room 310 at Moscone. You can meet the EDA luminaries of tomorrow, and they can brag on their work - and, no doubt, on their advisors as well. Warning - you will be carded along with the rest of the attendees if you ask for a beer.
SPIRIT Consortium Events at DAC - This from Jayne Scheckla, Marketing Programs Manager for System-level Engineering at Mentor Graphics: On behalf of The SPIRIT Consortium, I would like to encourage you to attend our annual general meeting, behind held in conjunction with DAC on Monday, July 24th, from 6:00 PM to 8PM, at the San Francisco Marriott in Salons 1, 2, and 3. The presentations and discussion of roadmap plans will last an hour, followed by a cocktail, networking, and demonstration hour. Demonstrations will include: ARM's Nizar Romdhane talking about "Multi-stage design-flow integration from SystemC, to RTL, to prototype-board debug configuration using IP-XACT"; Beach Solutions' Colin Tattersall talking about "IP-XACT used to drive IP verification using Beach Solution's EASI-Studio tool"; Denali's Sean Smith talking about "Denali's Blueprint demonstration: SystemRDL and IP-XACT - language synergy for combining IP"; Esterel Technologies' Arnaldo Malavasi talking about "ESL synthesis with Esterel Studio and The SPIRIT Consortium specifications"; Improv Systems' Cary Ussery talking about "Integration and Configuration of The Improv Media Platform Using IP-XACT"; Mentor Graphics' John Wilson talking about "Platform Express: An IP-XACT design environment for system level design and verification"; Philips Semiconductors' Marino Strik talking about "Creating an efficient derivative design flow using the IP-XACT specification"; Poseidon-Systems' Bill Salefski talking about "Performance Matters: Standards help in analyzing the performance characteristics of an embedded system"; and Synopsys' John Swanson talking about "An Integrated IP-XACT Design and Verification flow with Synopsys' coreAssembler and DesignWare IP." I think it's worth sticking around for all of these folks as long as it's open bar the entire hour!
Srinivas Raghvendra, Senior Director of DFM Solutions at Synopsys - At DAC, expect to see a great deal of emphasis on DFM at 65-nanometer-and-below geometries. Designers at 65 nanometers, and below, need DFM tools that will accelerate time to yield, and it's imperative that those design tools also be manufacturing-aware. Since true DFM spans the entire design-to-silicon flow, Synopsys will be highlighting our comprehensive suite of DFM solutions at DAC and demonstrating how we're bridging the gap between design and manufacturing to address the yield challenges facing the industry.
Stephen Maneatis, CEO at True Circuits - We are a leading provider of analog and mixed-signal IP for the semiconductor, systems, and electronics industries. We've recently announced that our Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) hard macros are available for TSMC and Chartered 65-nanometer processes, and have been shipping to customers for use in their designs. These high-quality, low-jitter PLL and DLL hard macros are designed by TCI, easily integrated, and fully supported, so customers can reduce both design and silicon risks. The hard macros are pin-programmable, highly process tolerant, reusable, and available in a range of frequencies, multiplication factors, sizes, and functions to suit a wide variety of standards and chip applications.
SystemC Users Meeting - The North American SystemC users are meeting from 1:30 PM to 6:00 PM on Monday, July 24th, in Room 200 at Moscone Center. But before they do, there's an OSCI meeting to enjoy over lunch
SystemC / SystemVerilog - You need to know more about SystemC / SystemVerilog interactions, and therefore you'll want to be in Moscone Center, Rooms 200 & 210, on Monday, July 24th, from 11:30 AM to 1:45 PM when Johny Srouji, who is Chair of the IEEE SystemVerilog Working Group and Accellera Technical Chairman, and Stuart Swan, who is Technical Chair of the IEEE SystemC Working Group, address the topic. I believe they will be wearing matching ties as a sign of solidarity across these complex language paradigms.
SystemVerilog Panel - Free breakfast is yours if you come to the Wednesday, July 26th, 7:30 AM to 9:30 AM Accellera panel titled: "Mission Possible III: SystemVerilog in Action!" at the Marriott Hotel, Golden Gate Room A1. The premise of the discussion: SystemVerilog is now recognized as "the most impactful new electronic design automation standard delivered to the engineering community in almost 20 years - a tremendous testament to the co-operation and hard work of a large number of technologists from many major EDA, semiconductor and services companies. SystemVerilog is already widely in use to increase design and verification performance, productivity and quality with broad vendor support and user adoption gaining momentum." I've been told this panel will be exciting - and I know that's true because ARM's John Goodenough, TI's Somdipta Roy, Sun's Thomas Thatcher, Freescale's Mike Burns, and Intel's Matt Maidment are all fun guys - plus, they're morning people who promise to chase away any cobwebs left over from Tuesday night's Denali excesses. I'll be moderating and you all should plan to join us. Please note, however, it's BYOB in the category of Alka-Seltzer and tomato juice.
Tensilica's Paint-by-Numbers - Kudos to Tensilica for leveraging DAC for the sake of culture. They're raising money at their booth for the San Jose Ballet. If you drop by and participate, you'll help Tensilica in their noble effort. It sounds like fun, and I'm going to try to get there to pitch in. Hope you will, too.
UML at DAC - If you missed it, there was an entire EDA Weekly posted on June 19th, that was devoted entirely to the topic of UML and ESL, etc., and the tutorial that will be taking place all day Sunday, July 23rd, at the outset of the conference. Please take a moment to read that column, and consider attending this forward-looking, daylong discussion. I sincerely believe you will not regret it.
Verification - There's a great panel happening on Thursday, July 27th, from 10:30 AM to 12:00 Noon in Rooms 306-308 at Moscone Center. The topic is, "Building a Verification Plan; Trading Brute Force for Finesse." Multiple, well-known luminaries from the world of verification will be one the panel: Harry Foster from Mentor Graphics, Janick Bergeron from Synopsys, Andy Piziali from Cadence, Raj Mitra from TI, Doron Stein from Cisco, and Catherine Ahlschlager from Sun. I spoke at length last week with Craig Cochran, Vice President of Marketing at Jasper Design Automation, and Rajeev Ranjan, CTO at Jasper, about the topic of this panel, and the importance of the discussion. They told me that half, if not more, of the battle for successful verification in a project is won by having a verification plan in hand before forging into the unknown territories of product development. We will hear more from Craig and Rajeev on the topic in conjunction with details from the panel discussion at DAC in my post-DAC wrap-up. Meanwhile, I look forward to seeing all of you on the 27th!
VHDL at DAC - The VHDL Technical Committee Meeting follows on the heels of the OVL meeting, Wednesday, July 26th, from 3:30 PM to 5:30 PM, also at the Marriott Hotel, in Golden Gate Room B2.
Will Ruby, Vice President of Marketing at Golden Gate Technology - Golden Gate Technology will be demonstrating an improved version of its power reduction and optimization software, PowerGold (formerly called Power Optimize Gold), at DAC. The software complements industry-standard cell physical design flows delivers 10-to-20 percent or more power savings, and offers faster run times than the previous version.
Women in EDA - Are there any? Well, of course there are - but after decades of attempting to encourage young girls to pursue degrees in science and engineering you would think we would be farther along. But we're not, and hence the Workshop for Women in Design Automation continues to serve an important role at DAC. This year, WWINDA will take place on Monday, July 24th, from 9:00 AM to 12:45 PM in Moscone Center, Room 302, followed by lunch. Workshop chair is Dataquest's Daya Nadamuni, and vice chair is Virage Logic's Sabina Burns. The topic of the day will be applying the 80/20 rule to balancing career and non-career related demands on time. The keynote address will be delivered by nVidia's Reynette Au, plus this year's recipient of the Marie R. Pistilli Women in EDA Achievement Award, IBM's Ellen Yoffa, will be honored. Yoffa will also be featured, along with Cadence's Jan Willis and the Anita Borg Institute's Telle Whitney on a DAC Pavilion Panel on Tuesday, July 25th, at 2:00 PM. I will be moderating that discussion, where the panelists will talk about professional development and the challenges that come over the course of a successful career.
San Francisco is my hometown, so a few quick rules. It's never Frisco, it's very cold in July, and any references to hippies, the Summer of Love, or anything even vaguely homophobic are tiresome and never funny. But, let me assure you - no matter what comments you let drop, they won't detract from the eternal magic of The City. They will only show you to be a provincial who doesn't get what Northern California is all about. This is a place of tolerance, culture, and innovation. Silicon Valley may be the brains of Northern California, but the heart of the place is definitely in San Francisco, high on a hill, above the blue and windy sea. So, come to DAC, and enjoy this lovely, lovely place. I do believe it is the most beautiful city on earth.
Addendum on DFM
Prashant Maniar, Chief Strategy Officer, Stratosphere Solutions - Prashant submitted these answers to questions he saw listed in the July 3rd issue of EDA Weekly. They are useful here as an addendum to The Buzz, as a reminder of the issues that will be on the table multiple times at DAC.
If you're making money in the DFM market, briefly tell me what technology you're selling. Please be succinct. I'm easily confused here (not kidding!).
Stratosphere Solutions is vending silicon-proven tools and applications for yield ramp, specifically focused on characterizing parametric variability, a rapidly growing yield loss mechanism at sub-100-nanometer process technologies. Our technology provides very high resolution analog measurements of critical process parameters in very small amounts of silicon real estate.
Has the skepticism over DFM subsided a bit over the last 18 months as far as being a revenue-generating business opportunity - in other words, are DFM vendors silencing their critics by actually making some money?
Yes and No. Several DFM (non-OPC/RET/TCAD) vendors are generating limited amount of revenue. How many vendors can turn it into a sizeable, repeatable revenue stream and significantly profitable business is yet to be seen. The number of companies offering litho-centric DFM tools is large and this segment will succumb to price pressure sooner than later (the fate of many sustainable, i.e. non-disruptive, innovations in EDA). Companies that deliver truly disruptive technologies in a manner that does not disrupt the design flow will, in the long term, demonstrate strong financial health.
If OPC/RET and wire spreading have been around for a while, what is the 'new' part of DFM that seems to be generating so much interest?
DFM is being used as a “catch-all.” The majority of the DFM companies are focused on modeling lithography and CMP, i.e. systematic, effects, and bringing them into the design flow. Some are focused on point tools for characterizing and modeling parametric variability, and analyzing its impact on design performance. We look at it from a holistic design for (parametric) yield (DFY) perspective rather than just manufacturability. The exciting aspect of taking this direction is building an innovative pattern-oriented, empirical model based, statistical tool infrastructure (for manufacturers as well as designers) and integrating it into the design and manufacturing flow.
Why did Numerical Technologies get acquired by Synopsys? Why wasn't there enough of a market to offer an opportunity to IPO, or at least to stay an independent entity?
I can't comment on the deal since I wasn't involved. However, an appropriate question asked, especially by investors, is: Can a DFM/DFY company function as a stand-alone entity over the long term? Yes. With the right strategy, a DFM/DFY business can be highly profitable $100M+ business.
Is DFM still in the 'educational' phase, both with respect to engineers and the VC community?
Definitely! The notion of yield improvement/DFM/DFY is evolving, albeit rapidly, both technologically and market-wise. Phase-0 was about RET/OPC. Phase-1 has been about designers becoming more educated about the process (e.g., litho, CMP, etch, etc.). The next phase will be about moving from commonplace edge-based and deterministic approaches to a pattern-based statistical model driven world.
If you had $10 million tomorrow from an investor, how would you spend it enhancing your DFM offerings, or what additional tools would you buy from your DFM vendor, if you're a user?
In addition to our current product offerings, we have built significant algorithmic IP in areas such as statistical modeling and analysis. We would spend that money in productizing that IP and working with customers to accelerate adoption of those products. So we would spend proportionally on R&D, AEs, and marketing. We also need to invest in market education for the benefit of these statistical methods for parametric yield improvement.
Are the in-house DFM tools really the majority of those being used today ... i.e., is there really a market in the EDA space for vendors other than the big 3 or 4 who have the channel and the R&D budgets to pursue expensive advancements in this highly technical area?
In the absence of commercial tools, semiconductor companies do invest in building in-house tools. However, most of the innovation in EDA has, and will continue to, come from start-ups. Semiconductor companies have recognized this fact and are working with emerging start-ups to get early access to innovative technologies. These customers are also driving integration of new tools into their existing design flows.
Will the next generation of designers not need to worry about DFM because they'll be working more and more on reconfigurable or programmable platforms?
The need to account for the impact of process variations on performance and parametric yield will exist and grow for designers of sub-100-nanometer ASICs, as well as programmable or structured parts.
To clearly articulate the business value proposition of DFM/DFY, you need customer proof of yield improvement. We have been amazed at how well customers comprehend the value of DFM/DFY tools and the direction vendors must take, which is not necessarily the traditional route vendors have taken, or investors have advocated, in the past.
Editor's note: Thanks to Kris McArthur for the great photos of San Francisco included here. They are in order: The Golden Gate Bridge, The Japanese Tea Garden in Golden Gate Park, The Transamerica Pyramid, San Francisco from Marin County, The Botanical Gardens, A view from the Marin Headlands, and Lombard Street - the crookedist street in the world.