Hot Chips, Cool Books, Brainiacs & Workaholics Abound
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Hot Chips, Cool Books, Brainiacs & Workaholics Abound

Although the weather in other geographies of late has been record breaking in terms of heat, rain, hurricanes, and monsoons – here in Silicon Valley it’s been one of the bluest, mildest, most gloriously beautiful summers imaginable. Anybody in their right mind would have taken the entire month of August off just to bask in the delicious perfection of it all, but happily the work ethic is up and running in Silicon Valley.

Last week alone, saw a plethora of events. The Fabless Semiconductor Association hosted a lunchtime panel of distinguished speakers at the Santa Clara Convention Center talking about the future of innovation. The Hot Chip guys hosted a bunch of chip-design brainiacs on the sun-dappled Stanford campus, followed straightaway by the Hot Interconnect guys. Sun Microsystems hosted customers and press alike on their own sun-dappled campus in Santa Clara to announce their new Eco-Everything initiative. Both Synopsys and Mentor kept EDA analysts and press busy with their quarterly revenue conference calls and the subsequent jubilation in the market, Cadence acquired Clear Shape, and Cadence and Mentor together announced a cooperative verification initiative.

Are all these people crazy? Don’t they ever look out the window and think about heading out to the beach with an umbrella and a good book? Apparently not, so please read on to see what’s been going over the last several weeks. (First click Print Article to see the total text w/o interruption.)


Chapter 1: Blessed are the Peace Makers – Mentor & Cadence play nice

Cadence Design Systems and Mentor Graphics announced they will standardize on a verification methodology based on IEEE 1800-2005 SystemVerilog. Per the Press Release: “The [newly announced] Open Verification Methodology (OVM) will deliver a tool-independent solution [that] delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and [will] be available in source code format … The OVM library will be open source [under] the terms of an Apache 2.0 license, SystemVerilog IEEE-1800 compliant, and portable to any simulator supporting that IEEE standard.”

“The OVM and supporting class library include foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments, and reusable VIP in SystemVerilog … Cadence and Mentor have collaborated to ensure that the OVM will run on their simulators, and will enable backwards compatibility with their existing environments, AVM from Mentor Graphics and Incisive Plan-to-Closure Methodology (URM module) from Cadence.”

Sanjay Srivastava, President and CEO at Denali Software, endorsed the move via a Press Release: "The industry is clearly embracing SystemVerilog for functional verification, and this is further accelerated with an open source methodology that offers increased interoperability within the EDA ecosystem. Portability is key, and the OVM addresses this with multi-vendor support.”

Predrag Markovic,
President of HDL Design House, offered: "The OVM offers exactly what we have been looking for: a single open, robust, and interoperable verification methodology [that] greatly simplifies our development and support processes, and will speed up the delivery of VIP and verification environment components to our customers.”

From Robert Hurley, CEO at Doulos: "The commitment from Cadence and Mentor to offer an open verification methodology rooted in IEEE 1800 with transaction-level modeling support that is interoperable amongst EDA tools and supports interoperable VIP will be matched by our commitment to support customers globally with training to allow them to get the most out of the OVM."

The implications of all of this seemed potentially profound, so it was great to chat by phone on August 22nd with Stan Krolikoski, Group Director of Standards and Interoperability at Cadence, and Dennis Brophy, Director of strategic business development in the Design Verification & Test Division at Mentor Graphics.

Stan and Dennis go way back – over 20 years they told me – and were both involved, along with Gabe Moretti and Shrenik Mehta, in the coming together of VHDL and Verilog and the founding of Accellera. Stan has also been heavily involved in SystemC, and the founding and nurturing of OSCI. What Stan and Dennis don’t know about language standards and inter-industry cooperation probably isn’t worth knowing.

Stan said, “With the coming of verification IP we all saw great promise for SystemVerilog, but we also saw the three major EDA vendors, to a greater or lesser degree, each developing IEEE-compatible class libraries. Synopsys produced VMM, Cadence produced URM, and Mentor produced AVM. This [proliferation] wasn’t helping the industry, so we started talking with Mentor about combining our assets. Some of the people [involved] at Mentor had worked in the past with some of the people at Cadence, and so it became the natural thing to work together to develop a common set of class libraries that could be made available on an open and free basis to the industry. With all due respect to the small players in the industry, there are actually 3 [main worlds] in simulators. By creating OVM from Mentor’s AVM and Cadence’s URM, we’ve now made two-thirds of those worlds compatible.”

I asked Stan and Dennis why the third world wasn’t involved in OVM. Dennis said, “Synopsys has never wanted to go that way on the methodology side, but it’s been a natural thing for [Cadence and Mentor] to come together on this, because we look at the problem in the same way. Bringing our two bodies of work together to create OVM has not been a trivial [effort], but we also didn’t have to make radically large changes to the way we do things because we approach the problem in the same way. Now users common to both Mentor and Cadence, as well as verification IP suppliers, will get interoperability and portability in their test benches.”

I asked if this type of cooperation within the infamously competitive, contentious world of EDA was something to celebrate. Dennis said I was overstating the tension in the industry: “When two parties in the industry want to collaborate, they will. Fundamentally, we did not want to do anything in OVM that required private ways of interpreting SystemVerilog. [We used] the stock IEEE standard language, so all companies would have access [to the results].”

Stan added, “Under the Apache 2.0 license, there really will be no restrictions on what you can do with OVM. Mentor had already put AVM – a damn good piece of technology – out under that license and we were planning to go out with our Incisive Plan-to-Closure Methodology under open source, as well. Now Cadence and Mentor are providing interoperable and proven [technology] that will work with both of our simulators, [providing] great benefits across the industry to everyone including IP providers, consumers, and other EDA companies.”

“VIP is required,” Stan emphasized, “if we’re ever going to fulfill the vision of platform-based design. If we can’t get a VIP ecosystem to work, we’ll never succeed. With OVM, we’ve made sure that at the TLM-level SystemC and SystemVerilog can interoperate.”

To which Dennis added, “We’ve started to build communities that will allow VIP to become plug-and-play. The SystemC [people] have been working to define a TLM. Through OVM, Mentor and Cadence have now taken the concept and made it available in the SystemVerilog environment, as well.”

Stan added, “This ability to interoperate at the transaction level will help SystemC, [particularly] in companies where there’s mixed use of languages at a higher level.”

Similarly, Dennis said OVM will help SystemVerilog: “[Previously], companies creating VIP couldn’t afford to maintain business relationships with other companies, retarding the entire adoption of SystemVerilog. What Mentor and Cadence are doing here is to make the barriers to adoption as low as possible, and to live up to the promise of the SystemVerilog language. Also, in addition to the code, we’ll have two other important elements in OVM – documentation and a set of guidelines for the users. If users follow these guidelines, they’ll be able to interoperate.”

It all sounded so easy and sensible, I asked Stan and Dennis if there was a hint somewhere in there that OSCI and Accellera would soon become one. They both laughed out loud. Stan said, “We’re not merging! But both franchises – OSCI and Accellera – want to see the promise of SystemC and SystemVerilog [realized], and these standards are connected.”

Dennis seconded that motion and added, “The response to OVM from the customers has been fantastic on both the Mentor and the Cadence side. Our partners and our employees are just ecstatic that the two companies have risen together to collaborate.”

“In fact,” Stan added as the phone call came to an end, “the reactions from our customers have come in two flavors: ‘What took you so long?’ and ‘Finally, you listened to me!’”

Dennis and Stan both chuckled and signed off. Clearly, both Mentor and Cadence have been listening – not just to their customers, but to each other as well. Bravo to both companies for breaking down barriers in verification.


Chapter 2: Cool Books – Verification on both sides of the aisle

Speaking of verification, Mike Mintz and Robert Ekendahl have penned a beautiful pair of books you’re going to want to add to that beach bag and/or your library.

Hardware Verification with C++
– With broad strokes and fine prose, this textbook-quality tome, published by Springer in 2006, starts out with a defense of C++ as a verification language, discussing both the advantages and drawbacks, moves on to look at object-oriented programming, delves into issues of open source, drills down into the Truss verification framework and flow, enhances learning with specific examples, and waxes poetic about best practices in both design and verification using OO programming constructs. With coding suggestions and in-depth examination of coding samples, this book actually does belong in the beach bag – particularly if you’re one of the lucky ones who dreams in code and also dreams of coding better, faster, and cleaner. The book comes complete with a CD/Practitioners Handbook.

Hardware Verification with SystemVerilog
– In a natural companion text centered on SystemVerilog, Mintz and Ekendahl have published here in 2007 (also with Springer), the textbook that completes the set. A stand-alone book that can be enjoyed based on its own merits, it’s a particularly powerful learning tool when studied in conjunction with the Mintz/Ekendahl 2006 text on verification with SystemC. Mirroring the earlier book, the merits of SystemVerilog as a verification language are evaluated here in this new offering, along with a discussion of OO programming, classes, coding, correct-by-construction techniques, Truss frameworks and flows, and a discussion of both block-level and chip-level testing.


Chapter 3: More M&A in DFM – Cadence snaps up Clear Shape and Blaze chimes in

Fast on the heels of Mentor Graphic’s acquisition of DFM vendor Sierra Design Automation in June, Cadence Design Systems has announced the acquisition of Clear Shape Technologies.

Per the August 16th Press Release: “Combined with Cadence's existing DFM methodologies and capabilities, the acquisition uniquely positions Cadence as the only EDA company that can deliver manufacturing awareness and lithographic correctness for all layers in an IC from transistor through interconnect, in designs ranging from SoCs to full-custom and all design domains including analog, digital and mixed signal.”

The Press Release also contains quotes from Clear Shape President & CEO Atul Sharan: "We think there's a lot of momentum to be gained by integrating Clear Shape's predictive, manufacturing-OPC-tool independent, validated-in-silicon lithography capabilities into the Cadence DFM environment. We've always believed that the combination of rule-based and model-based technologies is the future of DFM, and Cadence shares this belief. This synergy allows us to provide the industry leading support for the widest range of advanced IC designs."

Synergy notwithstanding, Dave Reed, Vice President of Marketing & Business Development at Blaze DFM, offered answers by email to the following questions regarding the Cadence/Clear Shape deal:

Q – What's still missing in the Cadence flow even after the Clear Shape acquisition?

Dave Reed – Cadence has not been very strong in the DFM area so far, so they still have many holes, in my opinion. Clear Shape does bring them hot-spot checking, which is important for 65 nanometer-and-below designs. They will probably work on integrating that into one or more of their routers.

From what I've heard, the Clear Shape acquisition did not bring Cadence a litho solution with the accuracy needed for a serious electrical DFM offering, which we think is the most interesting area of DFM. The litho-accuracy requirements in that area are pretty high.

Q – Why don't the big EDA vendors just develop their own internal solutions – why do they need to buy them?

Dave Reed – Any vendor, large or small, should always be considering Make vs. Buy when developing technology. We’ve done that ourselves at Blaze, bringing in external technologies for database (from OA) and litho (from the Aprio merger), for example. There's nothing wrong with this.

One observation, however, is that the big EDA companies tend to look at problems in terms of how their existing tools can address them, rather than thinking in terms of how to best solve the problems. I think this is a somewhat inevitable consequence of how these companies are organized. The tool groups keep looking for things for their tools to do. For example, every problem becomes a P&R problem to the P&R group, and so forth.

Q – How large is the DFM market now that several acquisitions have occurred in the last few months?

Dave Reed – The DFM market continues to grow. Some very serious problems with the design-to-manufacturing handoff are just starting to be felt at 90 nanometers and below, and this is driving customers to adopt DFM solutions. The consolidation is motivated in part by the need to bring complete DFM solutions together. Some of the companies that are now being acquired had chosen to focus primarily on DFM analysis. These could never be stand-alone companies – analysis is just a means to an end.

Traditionally the largest value is commanded by companies that can do something with analysis results – in order words, provide some kind of optimization. Here is where we took a different tack at Blaze. We've been focused from the start on providing a complete electrical DFM solution that includes optimization. We believe this is the basis of a stand-alone DFM company.

Q – Can a DFM vendor have any other exit strategy besides acquisition?

Dave Reed – We believe that there is room for one freestanding DFM solution provider. This is a very big, very demanding area and we think that a company (like Blaze) that focuses on providing a complete DFM solution will be able to out-compete the broader EDA solution providers. Rather than seeking to be bought, Blaze has been a player in the acquisition market, and we will continue to keep our eyes open for opportunities.

[Editor’s note – You can read more from both Atul Sharan and Dave Reed in the May 2007 EDA Weekly article, “DAC & DFM – Once More, with Feeling.”]


Chapter 4: $$$ – Synopsys & Mentor shine

If you’re addicted to the overlap between business and technology, August 22nd and 23rd met all your needs with back-to-back earnings calls from Synopsys and Mentor Graphics – phone calls that were distinctly upbeat.

Certainly if the market’s any indicator, investors and (most) analysts loved what’s happening at Synopsys. SNPS moved up markedly on August 23rd, the day after Q3 2007 results were announced. Quarterly revenues for Synopsys came in at around the $304 million range, a 10-percent increase compared to the same period last year, which puts Synopsys on track to deliver a tasty $1.2 billion 2007, or better.

The quote attributed to Aart de Geus, Chairman and CEO at Synopsys, in the Press Release said it all: "In the third quarter, we delivered strong earnings growth and cash flow and entered into very important customer alliances. We are confident about our position, and look forward to ending the year strongly and well-positioned for 2008."

Dr. de Geus was equally positive on the phone call, citing Synopsys’ position in low-power, DFM, IP enhanced with the purchase of the MOSAID assets, verification enhanced with the purchase of ArchPro, and the recently announced deal with Intel. He also noted recent volatility in the larger markets and moved to reassure listeners that Synopsys was stable and essentially unaffected by that volatility, even though people shouldn’t over interpret any particular quarter. “Things can be somewhat lumpy at times,” de Geus said.

Meanwhile, Mentor Graphics thrilled fans, analysts, and investors with their Q2 earnings reported out on August 23rd – MENT shot up 18% on August 24th! With Q2 revenues coming in at $205 million, the numbers were up 15% over the same period last year, putting the company on track for an $820 million fiscal year in 2007.

Press Release quotes attributed to Mentor Chairman/CEO Walden Rhines were ecstatic: “During the quarter, we saw strength across all of our system-related product lines. In addition to strength in more traditional systems design segments like FPGA and PCB design, we also saw significant strength in automotive design and ESL products.”

Real-time soundbites from the conference call were equally exultant. Mentor President Greg Hinckley evoked Gary Smith and EDAC during the call to support the thesis that the EDA market is moving up and to the right and to insist that Mentor‘s contributing to that trend. In addition, Hinckley noted that anything that even “touches” system design is heavily in demand, and hence Mentor benefits because the company’s so heavily positioned in ESL. He also crowed, “Our RET business is booming. We’re well positioned in design for manufacturing!”

Rhines added to the optimism on the call by insisting that neither Mentor’s newly released Veloce product line, nor Mentor’s newly-acquired Sierra Design Automation Olympus technology, face any significant competition in a solutions-hungry marketplace.

Rhines also commented on the Mentor/Cadence OVM announcement : “We really don’t need 3 different verification methodologies in the industry. Mentor has been in the lead with our AVM technology. By joining with Cadence’s URM to create OVM, we’re providing what the industry wants, namely open standards and consolidation of industry resources around fewer standards.”

By the way, if you think there’s nothing substantive that takes place during an earnings call, I’d invite you to mosey on over to the Synopsys and/or Mentor websites to listen to these archived earnings calls. They’ll be available for a few more days and are actually quite instructional. If you do, see if you sense a greater willingness on the part of the analysts to grill Mentor executives on their numbers versus their treatment of Synopsys execs. Perhaps it’s just my imagination, but it sure seemed that way to me.


Chapter 5: Hot Chips & Brainiacs – Cores & snores multiply like rabbits

There were over 600 hard-core chip design folks in and around Stanford’s Memorial Auditorium from August 19th to 21st attending the 19th annual edition of Hot Chips. Conference organizers told me it was the largest attendance since the bubble burst in 2000. I caught 4+ hours of the event on Monday, the 20th, and several more hours on the 21st.

Hot Chips is a single-track conference, so if you just plunk yourself down in the auditorium you’ll catch all the action. Among the speakers there, I heard 30-minute presentations from Erik Lindholm from NVIDIA talking about the GeForce 8800, John Nickolls, also from NVIDIA, talking about computing on GPUs, Prof. Wen-Mei Hwu from the University of Illinois talking about programming parallelism, Mike Mantor from AMD talking about the Radeon HD 2900 and graphics shader architecture, and Yatin Hoskote from Intel talking about a prototype processor with 80 cores. I also heard Verghese George from Intel talking about the 45-nanometer Penryn.

In all of these presentations, we were looking at detailed descriptions of chips that ranged from 550 to 700 million transistors, monsters with anywhere from 300 to over 2000 pins, performance metrics ranging from 575 GFlops/sec to upwards of a TeraFlop, dozens of on-chip GPUs, with and without CPUs, and mind-boggling numbers of available threads, anywhere from thousands to the tens of thousands. It’s technology that’s practically sci-fi in its scale and potential for computational and graphics-processing power.

Unfortunately it’s warm in Palo Alto at this time of year, so when you combine a packed auditorium, too-little air conditioning, too many laptops, and a big mid-day lunch, you often get a lot of snoozing across the room. That’s not to say the chips themselves aren’t hot, but engineering managers/technical session speakers aren’t always the most gifted when it comes to dramatics and oratory, so the splendor of what‘s been accomplished can be masked by a lack of flair and a lack of air. After the fact, however, when the oxygen’s flowing once again and you review your notes, these ginormous chips can be seen for what they are – truly astonishing …

And distinctly underutilized.

Illinois’ Wen-Mei Hwu, the most dynamic of the speakers I heard at Hot Chips, nailed it when he said most programmers today only understand their portion of a larger application, so the algorithms need to be re-designed and the programmers re-trained to see the big picture and take advantage of all of the thousands of threads the hardware is offering.

Hwu’s research on a variety of applications, however, indicates it’s easier said than done to get software developers to fully appreciate and utilize the massive features being thrown their way. Optimizing shared resources, accessing local and global memories, and attending to what he describes as “real, but rare dependencies” are all part of the learning curve that software guys will have to surmount before the hardware realizes its full potential.

Standing amidst the brainiacs outside of MemAud during one of the coffee breaks, I heard one guy summarize the problem even more succinctly than Dr. Hwu, “The thing is,” he said to the guy standing next to him, “Programmers just really don’t know how to parallelize their programs. It’s as simple as that.”

So, clone away you clever cores, but know you’ll have to wait a spell before your dreams of grandeur come to fruition.


Chapter 6: Stalled Industries – Glum Chums at FSA

Ten miles south of Palo Alto, it was all glumness and gloom at the FSA luncheon/panel discussion that took place in a remote corner of the ghostly, empty Santa Clara Convention Center on Tuesday, August 21st. What a relief to leave there, after what felt like a 2-hour wake for the fabless semiconductor industry, and return to the technical gravitas and intellectual oomph of the hundreds of real (albeit snoozing) engineers considering real technology back at Hot Chips that afternoon.

Don’t take my word, however, for the general tenor of the conversation at the FSA luncheon. You can read my version of the transcript posted to EDA Confidential and see for yourself. The fact that panel moderator Brian Fuller, now working in PR, opened the panel discussion with the statement – “The industry is dead” – says it all. Although Fuller later told me he was simply attempting to jump-start the conversation by being provocative, nobody actually disputed his sentiment during the entirety of the 90-minute panel discussion that followed, short of one contrarian VC panelist and his protest was only a murmured one.

Yes indeed, the times they are a-changing – or depressing – or both.


Chapter 7: Eternal Sunshine of the Spotless Mind – Innovate, Act & Share

Luckily before I got to the FSA on August 21st, I spent the morning at sunny Sun Microsystems nearby where everything was goodness, lightness, eco-responsible, open source, and humus on pita bread, served up with rock music and slim, trim Silicon Valley techno-execs – specifically Sun CIO, Bob Worrall, Sun VP of Eco Responsibility, Dave Douglas, and Sun CTO, John Fowler – all speaking to the art of Doing More with Less: less energy, fewer dollars, and smaller spaces.

Sun invited a range of customers, press, and local community leaders onto their Santa Clara campus to celebrate the ribbon cutting of their new, highly energy-efficient datacenter – a facility that would make both Arnold Schwarzenegger and Al Gore jump for joy, and one of three such earth-friendly facilities Sun has opened so far this year. The other two are located in Blackwater, U.K. and Bangalore, India.

Between the opening hour’s presentation in the main auditorium – complete with testimonials from Silicon Valley Power – and the chance to stand out in the sunshine to see the actual ribbon being cut in front of the datacenter, it was as uplifting and downright appealing an event as I’ve been to in a long, long time. Kudos to Sun for marrying corporate profit motives with eco-citizenry, and packaging it up in a way that makes others think it’s really possible. They even apologized for dispensing bottled water to the attendees – how politically correct is that?

Naturally, Sun wanted us to know that their energy saving derives in part from a “technolgoy refresh” to the newest of Sun’s cool servers and cooler, denser chips. It also derives from aggressive evaluations of their global energy needs, and an open give and take with employees who have been willing to offer up cunning suggestions to cut back, reduce, condense, and even eliminate facilities outright if more optimal computational and data storage solutions can be found. Hence, Sun’s not only offering their hardware to the industry at this point, they’re also offering consulting services to help you and yours make your operations and facilities more eco-responsible, as well.

Per the Press Release: “Sun's Eco Responsibility Initiative is guided by three principles: Innovate, Act and Share. Sun innovates by making products and services that are both good for the environment and good for business. Sun acts by operating in an open, eco-conscious way. Sun shares by making information and technology available to others so that we can all move forward and participate in an increasingly sustainable way.” Nice!


Chapter 8: On the Road Again – Stuff to Do & See

Okay, enough about the past. Now it’s time to plan for the future …

Altium is holding a seminar road show in 16 cities across North America in the fall. Per the Press Release: “The sessions will unveil the powerful new features of Altium Designer and how they combine with Altium's Desktop NanoBoard reprogrammable development platform … Sessions will include a practical workshop to demonstrate the potential of FPGAs.” FPGA novice or expert, everybody’s invited.

ARM Developers’ Conference
comes to Silicon Valley October 2nd to 4th. ARM will undoubtedly have announcements at the show, plus there will be keynotes, food, booths, and all the other stuff that the EDA world knows and loves. You should plan on attending.

CDNLive! is Cadence Design Systems’ User Conference and it’s happening September 10th to 12th in Silicon Valley, and is part of the company’s global road show. Other mega-organizations providing sponsorship include ARM, IBM, TSMC, UMC, and the Common Platform group, among others.

EDA Tech Forum,
billed as “The Largest EDA Industry Event” and brought to you by Mentor Graphics and others including ARM, Altera, Lattice, and The MathWorks, announced keynote speakers for the September 12th event in Santa Clara. NASA’s Steve Squyres will present "The Spirit and Opportunity of Mars," and iSuppli’s Andrew Rassweiler will chat about "Apple iPhone - Design Choices and Comparative Analysis." They’re saying 4.5 million iPhones will ship this year. Do you have yours yet?

FSA is having their fall Suppliers Expo conference and networking event, also on September 12th in Silicon Valley. Expect booths, food, sessions, panels, and chotskies at this event, as well. Over 100 companies will be there. Will you be there, as well?

Novas Software announced its 2007 International User Conference, happening in a host of locations, will highlight "Enhancing Your Verification Productivity" with technical tutorials and case studies. If you’re in Shanghai, Beijing, Taipei, Hsinchu, Tokyo, Bangalore, Irvine, Austin, Santa Clara, Ottawa, Munich, or Bristol, you can catch the conference. Happily, “The conference agenda for each geographic region is customized to address the industry trends and specific interests of chip designers in US, Europe, and Asia. A major highlight for the U.S. and Asia programs is the tutorial – Getting the Most Out of SystemVerilog – developed by renowned expert and industry consultant Cliff Cummings.


Chapter 9: Calling all papers – DVCon & ISQED

DVCon 2008 – The 2008 Design and Verification Conference, sponsored by Accellera, is accepting paper, panel and tutorial submissions for DVCon 2008 (February 19-21, 2008 in San Jose). Appropriate topics? Low-power design and verification, formal verification, multi-clock verification, design and verification case studies, verification and design release management, functional coverage and verification data management, verification methodology and testbenches, and verification IP development. Proposals are due September 19, 2007

ISQED 2008 – The International Symposium on Quality Electronic Design (March 17-19, 2008, also in San Jose) is calling for papers in the following areas: manufacturing, semiconductor technology and devices; electronic design; and design automation and CAD. Proposals are due by September 30, 2007. Note that ISQED proceedings are published by IEEE and ACM.


Chapter 10: MIT Rocks!

“A 5-member team from MIT took home the winner's cup in the 2nd annual HW/SW co-design contest sponsored by the ACM-IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007) held in June in Nice.”

“The challenge was to implement a high-performance matrix-matrix multiplication (MMM) using any hardware and software design methodology targeting any FPGA development platform. Contest organizers Forrest Brewer from U.C. Santa Barbara and James Hoe from Carnegie Mellon provided a software-only starter reference solution for the Xilinx XUP development board … Nine teams of U.S. and European university students started the contest, with only MIT and Virginia Tech submitting a final design.”

The MIT team included Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer and Muralidaran Vijayaraghavan from MIT's Computer Science and Artificial Intelligence Lab (CSAIL). Not surprisingly, they completed their design using Bluespec’s ESL synthesis environment.

[Editor’s Note – As I’ve got a kid of my own laboring away in CSAIL at MIT, I’m distinctly jazzed about this particular news.]


Chapter 11: Can you say the alphabet backwards?

Zuken is now offering “free simulation design kits to assist with the integration of Altera’s new Arria GX FPGAs onto PCBs. Per the Press Release: “Zuken is quick to provide users of its enterprise-wide advanced packaging and PCB design environment, CR-5000, with simulation design kits that enable rapid and easy adoption of the devices.”

Xilinx announced collaborations with three fairly well-known EDA companies to promote “ultra-high capacity” FPGA design verification. Xilinx engineers say they’ll work with folks from Cadence, Mentor Graphics, and Synopsys to “define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today's 65-nanometer FPGAs as well as new and emerging FPGA architectures.“ Bruce Talley, VP of the Design Software Division at Xilinx, is pleased: "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our customers at 65 nanometers and beyond." Surely you’ll be hearing more about all of this going forward.

TEA Systems announced a new product that the company says “enhances the control of overlay and registration in advanced semiconductor manufacturing to minimize the influence on critical feature dimensions and yield. Vector Raptor is a seventh generation overlay control tool specifically designed to address the unique problems now being introduced by double patterning and sub-45-nanometer process-node technology …VR provides an object-oriented, fully-interactive graphic interface for advanced control of overlay/registration with matching to any format feature-profile or film data.”

Sonics announced the company’s Sonics SMART Interconnect solutions are available as library elements for Mentor Graphics' Vista and Visual Elite products. The companies say, “Mentor Graphics … now offers a complete configuration, analysis and verification of SystemC SoC platforms based on Sonics SMART Interconnect solutions … With this announcement, Mentor Graphics and Sonics are ensuring interoperability between Mentor's ESL design tools and the SystemC versions of Sonics SMART Interconnect solutions.”

Solido Design Automation has named Douglas Konkin Vice President of Product Development. Previously, he was Director of Software Development for fabless semiconductor company PMC-Sierra, managing the Saskatoon design center. Prior to PMC-Sierra he was VP of Technology at HyperCore Technology. Konkin has an M.Sc. In CS from the University of Saskatchewan and a B.Sc. in engineering physics from the Royal Military College in Ontario, Canada. He also served as a signal officer in the Canadian Army.

SMSC announced the EMC210x family of fan controllers, which the company says includes four devices that use RPM closed-loop control. SMSC also announced three new SMBus temperature sensors that allow systems to monitor high temperatures. Per the Press Release: “All devices are designed for 45 nanometers, and are typically associated with this level of monitoring and are used in flat screen TV, PC, printer and server applications.”

Silicon Image announced Paul Dal Santo has been named COO. Previously, Dal Santo was VP and GM at AMD. Prior to AMD, he worked at Motorola, as VP of GSM technology development managing a global team of 500+ people. Dal Santo has a BSE from Purdue and an MSE from the Illinois Institute of Technology.

Micronas announced a Mini-IP Camera development kit based on Micronas Cypher ESN7108A real-time streaming media encoder SoC. Per the Press Release: “The camera streams live audio/video content instantaneously over wired or wireless IP networks at D1 resolution. The Mini-IP Camera development kit is targeted for Small Office/Home Office and professional surveillance cameras where networked IP cameras are being utilized to prevent crime or record daily activities.” Have no fear, Big Brother is definitely watching.

Mephisto Design Automation (MDA) and AnSem announced “validation” of MDA’s M-Design tool capabilities. Per the Press Release: “M-Design was used to substantially improve the settling behavior of a complex switched-capacitor circuit. The original manual design failed to satisfy the target specification of settling time at the desired operating frequency, forcing the circuit to be operated at a lower frequency.” That’s why Martin Vogels, MDA CTO, is quoted: “By utilizing AnSem’s circuit expertise in combination with M-Design’s capabilities to fully capture design intent, the switched-capacitor circuit was sized for the desired specifications, most notably the settling time, and all specifications were met for all PVT variations.”

Mentor Graphics and IBM announced collaboration whereby Mentor’s Nucleus OS and EDGE Developer Suite for the IBM Cell Broadband Engine was “targeted” at IBM’s BladeCenter servers. Per the Press Release: “This marks the availability of the first full-featured real-time OS port for Cell/B.E. with integrated Eclipse tools and MAJIC multicore JTAG target connections … The Mentor Graphics products included in this collaboration are all of the Nucleus OS components, the EDGE Developer Suite based on Eclipse, and the EDGE MAJIC JTAG probe.”

Magma Design Automation reported revenue of $50.2 million for its Q1 2008 fiscal year, an increase of 22 percent over Q1 2007 fiscal year. Rajeev Madhavan, Magma Chairman & CEO of Magma, is quoted: “We delivered strong revenue growth and profitability in the first quarter. Customers are using our products for an increasingly wide range of applications – you can find chips designed with Magma software in just about every popular variety of electronic products made today. [Therefore], we are announcing increases in our guidance for both revenue and EPS.” I should have listened in on the phone call!

LogicVision has announced “major enhancements” to its ETCreate product family. The new release “provides comprehensive RTL insertion support for all BIST capabilities, including full support for the Verilog 2001 language, production releases of the company's memory built-in self-repair solution, ETMemory-Repair, and the company's ScanBurst at- speed scan solution.”

Please read on: “The ETCreate software provides consistent DFT rule checking for memory, logic and mixed-signal DFT insertion for both RTL and gate level design flows. The latest release is an important milestone, rounding out LogicVision's comprehensive support for the Verilog 2001 (V2K) language constructs, allowing customers to take full advantage of language improvements in V2K without any impact to the RTL insertion flow. The latest release also provides improved design file handling and management capabilities to further streamline the RTL flow.”

Kovac Software announced it has added “intelligent PDF file archiving and data exchange” to the company’s AutoTRAX EDA tool, which saves composite designs consisting of a schematic design and associated PCB together with a hierarchical page outline consisting of views of all the sheets and the PCB in the design … The PDF file can optionally contain either the schematic design and/or the PCB design.”

Kilopass Technology announced its XPM technology is available for 65-nanometer low-power (XPM-65LP) and general-purpose (XPM-65G+) processes. Craig Rawlings, Director of Marketing at Kilopass, is quoted: "With the introduction of our XPM technology for 65-nanometer processes, we are able to demonstrate that XPM memory technology is compatible with advanced CMOS geometries. Older technologies, like floating gate technologies, run into serious manufacturing challenges at geometries smaller than 130 nanometers. Since many of our customers understand these manufacturing hurdles, we are seeing a high demand for our IP, especially from customers designing products on advanced process geometries." Smart customers!

Group IV Semiconductor announced a “substantial” new round of investment led by Garage Technology Ventures Canada, with Applied Ventures, LLC, a subsidiary of Applied Materials, and existing investors Khosla Ventures and BDC Venture Capital. In addition, per the Press Release: “Group IV will also collaborate with Applied Materials to develop a low cost manufacturing process that will enable Group IV to accelerate its technology towards product commercialization and production … Group IV's solid-state light engines use a single-chip, AC-powered, silicon-based process that can deliver dramatic cost savings relative to conventional LED technologies.”

EVE announced it has formed a Consulting Services Division, with Donald Cramb in charge as Director, “responsible for customer services, applications and design solutions to support specific customer requests.” Previously, Cramb was a partner at ArchSilc Design Automation, Director of Services at Quickturn, and Vice President of Technical Services at both Virtio and Tharas Systems. Cramb started his career at Philips as a design engineer after earning a BSEE from the University of Edinburgh.

Ansoft Corp. announced financial results for Q1 of fiscal 2008. Revenue totaled $19.9 million, an increase of 15% compared to Q1 2007. Great results worth writing home about! Meanwhile, during the current quarter, the company announced the repurchase of 853,632 shares of its common stock.

Anchor Semiconductor and Dongbu HiTek announced “the increased applications and long term commitment to Anchor’s NanoScope DFM Platform … Anchor and Dongbu will also cooperate in the development of advanced pattern defect management systems to speed up the post-RET/OPC verification process and yield ramp-up through knowledge deposition and reuse utility.” Keeho Kim, Executive VP for Advanced Nano-Tech Development Team at Dongbu, is quoted: “After an extended technical evaluation of post-OPC verification tools available in the market place, Dongbu decided not only to continue its NanoScope usage but also expanded the licensing agreement to meet our rising business demand.”

Altera Corp. announced that its Cyclone III FPGAs were chosen by Silicon Video Systems (SVS) to build “the most compact and cost-effective multiviewer product on the market. Multiviewers are used in professional audio/video production, security surveillance and broadcast monitoring applications where multi-image display processing is required.”

ASSET InterTech and Agilent Technologies announced an extension of their joint sales, marketing and licensing agreement under which ASSET’s ScanWorks JTAG system has been integrated into Agilent’s 3070, Medalist i5000 and i3070 in-circuit test (ICT) systems. Per the Press Release: “Under the terms of the extended agreement, ASSET continues as Agilent’s preferred supplier of boundary-scan systems and intellectual property. Agilent provides worldwide support for ScanWorks on the Agilent i3070, 3070 and i5000 ICT systems.”

Agilent also announced its Momentum GX 3D electromagnetic (EM) simulator, which the company says is designed “to significantly expand the accuracy and range of passive circuit libraries, including parasitic models and entire circuits … reduce design steps [and] speed the design and verification process for complex RF and microwave passive circuit designs.” The product is integrated with Agilent’s Genesys EDA platform – technology acquired with Eagleware-Elanix.

Agilent announced, as well, a new parameter extraction “solution” for high voltage (HV) CMOS devices used in automotive, consumer, LCD and display driver products. Per the Press Release: “The HVMOS extraction package, for use with Agilent's Integrated Circuit Characterization and Analysis Program (IC-CAP) software platform, enables engineers to model HV CMOS devices using Synopsys' HSPICE simulator, HVMOS Level 66 compact model … The HVMOS model includes all relevant physical effects unique to high-voltage operation, including symmetric and asymmetric source and drain resistances, quasi-saturation, transconductance fall off at high-gate voltage, and self-heating effects.”

Agilent has clearly been busy, because the company also announced its latest Antenna Modeling Design System (AMDS) release verifies that handheld wireless devices are equipped with hearing-aid compatibility. Agilent’s Erwin De Baetselier is quoted in the Press Release: "By February 2008, all wireless carriers in the U.S. must ensure that 50 percent of their phones are hearing-aid compatible … We are leading the industry by offering HAC compatibility tests in our EM simulation environment, ensuring that designers of wireless devices will be able to meet these important and rigorous specifications." Who would have guessed?

Accellera announced the Board of Directors has approved Accellera’s Open Verification Library (OVL) 2.0 as an Accellera verification standard last month. Check out all the details on the Accellera website because the Press Release is happy to note: “OVL improves electronic design quality and supports Assertion-Based Verification (ABV) with Verilog, SystemVerilog, VHDL and the Property Specification Language (PSL).” What’s not to like?