Your ASIC design better work on silicon the first time!

Rapidly accelerating consumerization of electronic devices like cell phones and PDAs is causing chip design houses to hurtle to the finishing line, at break neck speeds, with their power feature packed ASIC designs. The design groups want to jam in fancy functionality on a single device like voice calls, MP3 player, GPS, web browser, digital audio/video camera, rich graphics and all this at the fastest possible access speeds while consuming the lowest possible power. These ASIC designs are pushed and shoved, through shorter and shorter design cycle times, taping out to the fabs to be imprinted on silicon while praying that the first silicon will be alive when it comes back from the foundry.

Herein lies the key. Designs which are not functionally verified beyond a string of doubt, ensuring that the design implementation conforms exactly to the architecture specifications and will work under all possible scenarios of usage at all times, never see their day on silicon. The first chip fails on the tester and then begins the endless loop of making hurried fixes to the existing design and taping out for the next spin at the foundry. Each of these masks are not cheap either, a company can easily cough up close to a million dollars in hard costs associated with a silicon respin and not talk about the delay in the product hitting the shelves- if at all.

An adequately verified ASIC design entails a mandatory spending of at least 50% of the total design effort on design verification. Yet, verification remains the weakest link today in most of the design cycles. Somehow, in the rush to get out to the market, thorough design verification becomes an optional task or a cursory effort to validate the design with a few test patterns that check for the design correctness in the simplest of cases that the product may ever be expected to prove functional by the consumer. Today, just placing a voice call may not be all that a cell phone is expected to do.

Not all is bleak however, there is a silver lining in that a few companies recognize the importance of putting robust design verification on a very high pedestal and believe that a design is only as good as its verification strategy. There are entire groups dedicated to hammering out the most appropriate verification methodology for the next generation wireless or networking products in such a fashion that a basic design bug gets caught very early in the design cycle and timing problems get detected during the physical design stage. All assumptions about the proper behavior of the design and the expected protocol adherence of the design are well documented as properties and checked for compliance by advanced rule checking tools. Various coverage metrics, which give a precise idea of the percentage of the design functionality exercised by the suite of architecture verification programs, are heavily relied upon to gauge completion of the verification effort. Design functionality which cannot be verified by simulating an actual application scenario, is verified statically by mathematical means. This has consistently helped leading semiconductor manufacturers’ go-to-market with the first rev of silicon.

In conclusion, it is extremely important for all ASIC design companies to recognize that there is no second chance when it comes to their design meeting all the specs in silicon and this can only be achieved by crafting out a well thought out, meticulous verification strategy that leaves nothing to imagination or hope of the silicon world not being that horrible after all.

By Sunil Kakkar who works at Freescale Semiconductor India Ltd and is the chief technologist for verification, for the India design center.


Rating:
Reviews:
Review Article
  • As Complexities Rise, Silicon Verification is Needed December 23, 2005
    Reviewed by 'Phil'
    I strongly agree that a comprehensive verification plan is required, but it should not end at the RTL verification step. You must plan during the architetcure stage to go beyond RTL simulation and emulation. You must plan to design-in debug structures for silicon. No amount of simulation will ever completely verifiy the functionality in today's complex SoC designs. Real-world, at-speed and in-system testing must be part of the first silicon verification process. The only way to achieve this is to build debug buses, observation points and reconfigurable control structures to allow for logic analysis, assertion testing and event-driven analysis. The overhead of these extra structures is easily mitigated by the enhanced bring-up of first silicon, not to mention the reduction in respins.

    Search the web and see where you can find "reconfigurable debug infrastructure."

    Thanks for the article and I hope this adds some value to others.

      9 of 9 found this review helpful.
      Was this review helpful to you?   (Report this review as inappropriate)


  • ... and on time as well... December 04, 2005
    Reviewed by 'Akiva Michelson'
    Sunil, Excellent article. I would add that a first-time quality is not the only requirement; Companies who want to win in the marketplace also need to concentrate on predictable schedules. This is slowly becoming the key differentiator between companies. Ace Verification has a world-class model for building a realistic predictable schedule for verification. Feel free to read the reference material on our web-site.

    .

      3 of 5 found this review helpful.
      Was this review helpful to you?   (Report this review as inappropriate)


  • Good article December 06, 2005
    Reviewed by 'Bruce_kang'
    It is quite good article, but it look like quite boring. I mean the authour shold gsupply examples or give some popular tools. We not only need to know it, but also need to know how to solve this problem

      5 of 8 found this review helpful.
      Was this review helpful to you?   (Report this review as inappropriate)


  • success of tape out now depends on the plan of verification January 24, 2006
    Reviewed by 'Bala'
    As Sunil (author of this article) mentioned, considering the complexity of the functionality added in today's ASIC, more than 50% of effort in a chip design goes to the functional Verification. So its obvious that verification becomes important component and clear cut plan is needed from the beginning of the project onwards to achieve the first time success. Also we need better verification plan, tools and methodology with better coverage metrics(which drives the verification) and constrain random capability(helps to automate most of the work) along with assertion based design methodology where you can use the assertions in static(formal) and dynamic simulations are needed. Reuse is another important strategy when we develop the testbench infrastucture for SoC verification to reduce the time to market. Thats the reason why we need high level verification languages(supporting OOP/AOP) like vera or e become handy for good verification. Now after the evoluation of system verilog as a unified language with testbench features and assertions may make our job more flexible if we adopt a good verification methodology and may help us to achive the first time success in shorter time.

      3 of 5 found this review helpful.
      Was this review helpful to you?   (Report this review as inappropriate)


  • Good Article November 28, 2005
    Reviewed by 'ankur arora'
    I think its a nice article on the current need of Semiconductor industry to deliver qualtiy products on time by virtue of good verification whcih is the need of the hour, and as we are moving to converging technoligies , higher end devices , Verification would be palying a major role in achieving our goal.

      2 of 2 found this review helpful.
      Was this review helpful to you?   (Report this review as inappropriate)


For more discussions, follow this link …
Aldec

Design Tips for Heavy Copper PCBs

Featured Video
Jobs
Senior and (less) Senior Design Verification Engineers for EDA Careers at San Jose and Austin, California
Principal Circuit Design Engineer for Rambus at Chapel Hill, North Carolina
Sr. Principal FPGA for Northrop Grumman Mission Systems at Morrisville, North Carolina
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Staff Engineer Digital-20003075 for Northrop Grumman Mission Systems at Redondo Beach, California
Upcoming Events
Embedded Vision Summit 2020 at Santa Clara Convention Center Santa Clara CA - May 18 - 21, 2020
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise