Rapidly accelerating consumerization of electronic devices like cell phones and PDAs is causing chip design houses to hurtle to the finishing line, at break neck speeds, with their power feature packed ASIC designs. The design groups want to jam in fancy functionality on a single device like voice calls, MP3 player, GPS, web browser, digital audio/video camera, rich graphics and all this at the fastest possible access speeds while consuming the lowest possible power. These ASIC designs are pushed and shoved, through shorter and shorter design cycle times, taping out to the fabs to be imprinted on silicon while praying that the first silicon will be alive when it comes back from the foundry.
Herein lies the key. Designs which are not functionally verified beyond a string of doubt, ensuring that the design implementation conforms exactly to the architecture specifications and will work under all possible scenarios of usage at all times, never see their day on silicon. The first chip fails on the tester and then begins the endless loop of making hurried fixes to the existing design and taping out for the next spin at the foundry. Each of these masks are not cheap either, a company can easily cough up close to a million dollars in hard costs associated with a silicon respin and not talk about the delay in the product hitting the shelves- if at all.
An adequately verified ASIC design entails a mandatory spending of at least 50% of the total design effort on design verification. Yet, verification remains the weakest link today in most of the design cycles. Somehow, in the rush to get out to the market, thorough design verification becomes an optional task or a cursory effort to validate the design with a few test patterns that check for the design correctness in the simplest of cases that the product may ever be expected to prove functional by the consumer. Today, just placing a voice call may not be all that a cell phone is expected to do.
Not all is bleak however, there is a silver lining in that a few companies recognize the importance of putting robust design verification on a very high pedestal and believe that a design is only as good as its verification strategy. There are entire groups dedicated to hammering out the most appropriate verification methodology for the next generation wireless or networking products in such a fashion that a basic design bug gets caught very early in the design cycle and timing problems get detected during the physical design stage. All assumptions about the proper behavior of the design and the expected protocol adherence of the design are well documented as properties and checked for compliance by advanced rule checking tools. Various coverage metrics, which give a precise idea of the percentage of the design functionality exercised by the suite of architecture verification programs, are heavily relied upon to gauge completion of the verification effort. Design functionality which cannot be verified by simulating an actual application scenario, is verified statically by mathematical means. This has consistently helped leading semiconductor manufacturers’ go-to-market with the first rev of silicon.
In conclusion, it is extremely important for all ASIC design companies to recognize that there is no second chance when it comes to their design meeting all the specs in silicon and this can only be achieved by crafting out a well thought out, meticulous verification strategy that leaves nothing to imagination or hope of the silicon world not being that horrible after all.
By Sunil Kakkar who works at Freescale Semiconductor India Ltd and is the chief technologist for verification, for the India design center.