August 22, 2005
Power Reduction wth Golden Gate Technology
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Power Plan Gold is the other product. The real value here is productivity. This product can automatically and very quickly create complex power grid. We have a demo that we show to prospects and I literally see their eye bulge and jaws drop at how quickly a complex grid can be created. The reason we can do this so quickly is because we found a unique technology called parametric template. We use it to define power grid layouts and implement them in a design. We support multiple voltage islands and multiple power supplies. We analyze the voltage drop, power and EM in the power grid and go in and fix the voltage drop.
A complex power grid can contain rings, stripes, rails, hookups, slotting, embedded macros, complex strapping structures, non-uniform distribution and so forth. We handle these complex situations very effectively.
What about voltage islands?
There's a lot of discussion right now and a lot of people trying this methodology to reduce power consumption. Essentially what this approach says is that I can run part of my logic at a lower speed and at a lower voltage. It's a good power reduction tool but it introduces a lot of issues and challenges in the physical implementation flow. You are dealing with two different domains. It becomes more complex but it is good viable tool. Golden Gate has automated the physical implementation of voltage islands. For example we automatically insert level shifters. These are special cells that are required to exist between blocks at different power supplies to be able to translate the voltage between the two blocks. Again you have a rule based approach. We have the ability to insert level shifters and verify the proper conductivity making sure no mistake is made.
The software also knows about rings and straps and so forth. We analyze the power grid. Then we go in and surgically fix the power grid. When we detect a voltage violation, we can fix the violation by changing the power grid only in the localized area. We don't over fix the power grid because the width of power straps and power buses and so on is important because it can get in the way of signal routing. This is where you can have routing congestion. By not over fixing the power grid we are avoiding that implementation problem.
As we try to reduce the power consumption and fix the power gird we can not depend upon the final analysis tools because farming out to those tools would bring down our turn around time. So our approach is embedded integrated analysis tools such as SI and voltage drop. We use them primarily as a gauge for power reduction, voltage drop and fixing the power grid. We have good correlation with the final analysis tools but are not claiming that they are the most accurate out there. In fact we are not in the business of providing such tools. This is purely an embedded technology within power reduction.
What is the price for these tools?
Power Optimizer Gold is starting at $185K. Power Plan Gold is starting at $150K for a one year license.
Would the typical customer have one or several licenses?
Typically one license per physical designer. Companies typically try to make sure that their place and route engineers have access to their tools at all times. What we are expecting is basically as many licenses as there are P&R seats.
Do you see any direct competition.
Possibly Sequence. They traditional strength is in power analysis. Their analysis is very accurate. They are now trying to move to power reduction. Their issue specifically in the physical implementation space is that they don't have P&R technology like Golden Gate does. The best thing that they can do is provide some directives, some configuration file to traditional P&R tools but that introduces a lot of iterations. The Synopsys router may not fully understand what the Sequence configuration file is really telling them to do. It will go out and try to do whatever it needs to do. That's one disadvantage they have on power reduction side. More traditional vendors like Synopsys, Magma and Cadence claim that they do something in power reduction but they are not really focused on power. They are not coming up with unique technology. We think we can work well with whatever they provide and we can add on top of that with our technology.
Any challenges moving to 65nm and 45 nm?
It is a challenge and an opportunity for us. At 65nm and 45 nm wiring becomes even more dominant for power consumption. If we reduce wiring capacitance and optimize the interconnect we can get even higher power saving. The challenge is the complexity of design rules. That's the main challenge I see there. I was talking to an engineer who said joking that design rules at those process nodes work like this: This wire has to be so far from that wire and so far from this wire except on Tuesday when it is different. These rules are getting very complex
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-- Jack Horgan, EDACafe.com Contributing Editor.
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