August 30, 2004
PCI Express
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Many OpenGL extensions have been defined by vendors and groups of vendors. The OpenGL Utility Library (GLU) provides many modeling features, such as quadric surfaces and NURBS curves and surfaces. GLU is a standard part of every OpenGL implementation. Also, there is a higher-level, object-oriented toolkit, Open Inventor, which is built atop OpenGL, and is available separately for many implementations of OpenGL.

The figure below gives an overview of the traditional graphics pipeline. Geometry (vertices, lines, polygons) and pixel data (pixels, images, bitmaps) take different routes.

OpenGL Pipeline Architecture


All geometric primitives are described by vertices. Even parametric curves and surfaces can be mathematically defined by a net of control points. Evaluators are used to calculate vertex properties such as surface normal, texture coordinates, colors, and spatial coordinate values. Per vertex operations include transformations (scaling, translation, rotation) and projections from 3D to 2D. Advanced operations for lighting and texture may also be applied. Primitives (lines, polygons, bit maps) are then assembled and clipped. Rasterization is the conversion of both geometric and pixel data into fragments. Each fragment square corresponds to a pixel in the framebuffer. Line and polygon stipples, line width, point size, shading model, and coverage calculations to support antialiasing are taken into consideration as vertices are connected into lines or the interior pixels are calculated for a filled polygon. Color and depth values are assigned for each fragment square. Blending, dithering, logical operation, and masking by a bitmask may also be performed.

Graphics Application (Digital Content Creation, CAD/CAM, ..) vendors build sophisticated software on top of OpenGL with interactive GUIs to define, edit and display models, animations and videos. Complex operations can be invoked by drag and drop techniques.

PCI Express Intro

All of the graphics products described above have in common that they are PCI Express based. Jim Pappas, Director of Initiative Marketing for Intel's Enterprise Platform Group, says “The graphics industry is expected to make a rapid transition to PCI Express taking advantage of the technology's increased performance characteristics”.

According to Jen-Hsun Huang, president and CEO at NVIDIA “The PCI Express transition is going to be an exciting time for the PC industry, stated. By aligning ourselves closely with Intel and helping define this new specification, we were able to engineer an innovative protocol engine, in HSI, that delivers the full-PCI Express feature set without any compromises. HSI and PCI Express will enable a new level of performance for high bandwidth applications like graphics and networking.”

“ Since the outset of the PCI Express initiative, our aim was to deliver a top-to-bottom family of PCI Express graphics cards to our OEM customers, hastening the PCI Express transition,” said Rick Bergman, Senior Vice President Marketing and General Manager, Desktop, ATI Technologies. “PCI-E is a major innovation in the computer architecture and there is a rapid transition in the market to this bus standard”

Note that while ATI and NVIDIA agree on the importance of PCI Express, the two companies are initially supporting PCI Express in very different ways: ATI will provide PCI Express compatibility with a new line of GPUs that offer native PCI-E support, while NVIDIA's first PCI Express efforts will use a High-Speed Interconnect (HSI) bridge chip to graft AGP GPUs to the PCI-E interface. This enables them to maintain parallel AGP and PCI-E GPU lines. The two firms are arguing in public over the strengths and weakness of the bridge approach.

Before describing PCI Express, we should review PCI that it is replacing.



PCI

Formed in 1992, PCI-SIG (originally formed as the Peripheral Component Interconnect Special Interest Group) is the industry organization chartered with the development and management of the PCI bus specification, the industry standard for a high-performance I/O interconnect to transfer data between a CPU and its peripherals. The PCI-SIG currently has more than 800 member companies.

The PCI (Peripheral Component Interconnect) bus structure introduced in 1992 has been the mainstay for over a decade. The original 33-MHz, 32-bit implementation delivers a peak theoretical bandwidth of 133 megabytes per second. Later generation of backwards compatible PCI bus specifications emerged to improve performance including a more recent 64-bit, 66MHz combination with a bandwidth of 512MB/s. PCI-X 1.0 with a maximum clock speed of 133 MHz was developed to increase the bus speed, reduce latency and improved protocols by doubling the bus width from 32 bits to 64 bits. PCI-X 2.0 specification extends the bus frequency to 266 MHz and 533MHz and adds advanced features like ECC.

Also introduced was the Accelerated Graphic Port (AGP) specification, which defined a dedicated high-speed PCI bus for graphics operations. The AGP bus offloaded graphics traffic from the PCI system bus and freed up bandwidth for other communications and I/O operations. The initial version of AGP was a 32-bit bus running at 66 MHz with a peak data transfer rate of 266 MB/s. AGP has evolved to AGP2X, AGP4X, and finally today's AGP8X, which operates at 2.134 gigabytes per second (GB/sec). In addition, Intel recently added dedicated USB 2.0 and Serial ATA links to the Southbridge in its chip sets, further reducing the I/O demands on the PCI bus.

Comparison of Bus Architecture Performance


The PCI architecture is shown in the diagram below.

PCI Architecture


Note the Host Bridge is often referred to as the Northbridge, while the I/O Bridge is referred to as the Southbridge. The Northbridge connects to fastest devise, namely the CPU, memory and graphics. The Southbridge bridge routes traffic from the different I/O devices on the system: the hard drives, USB ports, Ethernet ports, etc. to the Northbridge and onto to the CPU and/or memory. Because the PCI is not fast enough for some devices, the trends has been to attach interfaces (SATA, USB) directly to the Southbridge. Thus we now have collection of specialized buses of different protocols and bandwidth capabilities.

The demands of emerging computing and communications platforms exceed the capabilities of the traditional 32 bit, 33 MHz PCI bus. Technical innovations such as 10 GHz+ CPU speeds, faster memory, higher-speed graphics, gigabit networking, 1394b, and other applications will drive the need for much greater internal system bandwidth. For example, both 1394b and Gigabit Ethernet require bandwidth that exceeds PCI's current shared 133MB/sec maximum bandwidth. The general consensus is that PCI and AGP have reached their limits while the demand for increased performance and bandwidth only increase. The PCI bus cannot be easily scaled up in frequency or down in voltage. In addition, the PCI bus does not support features such as advanced power management, native hot plugging/hot swapping of peripherals, or Quality of Service (QoS) to guarantee bandwidth for real-time operations. Finally, all of the available bandwidth of the PCI bus is limited to one direction (send or receive) at a time.



PCI Express (PCEi)

PCI-SIG (the Peripheral Component Interconnect Special Interest Group), defines PCI Express as "...an open specification designed from the start to address the wide range of current and future system interconnect requirements of multiple market segments in the computing and communications industries. The PCI Express Architecture defines a flexible, scalable, high-speed, serial, point-to-point, hot pluggable/hot swappable interconnect that is software-compatible with PCI."

PCI Express (formerly 3GIO) is a new I/O technology that is compatible with the current PCI software environment. PCI Express defines a packetized protocol and load/store architecture. Its layered architecture enables attachment to copper, optical, or emerging physical signaling media. PCI Express uses an embedded clocking scheme to enable better frequency scaling and provides many advanced features as well as innovative form factors. It can be used for chip-to-chip and add-in card applications to provide connectivity for adapter cards, as a graphics I/O attach point for increased graphics bandwidth, as well as an attach point to other interconnects like 1394b, USB 2.0, InfiniBand Architecture and Ethernet.



You can find the full EDACafe event calendar here.

To read more news, click here.


-- Jack Horgan, EDACafe.com Contributing Editor.




Review Article Be the first to review this article
Aldec


Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
What’s on Tap from the ESD Alliance? Plenty! Read On …
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating IP and SoC Development
Jobs
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
ASIC SoC Verification Engineer for Ericsson at Austin, Texas
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
ASIC Engineer for Amazon at seattle, Washington
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
Upcoming Events
SEMI MEMS & Sensors Industry Group (MSIG), MSTC 2021 at United States - Apr 13 - 15, 2021
Simulation World at United States - Apr 20 - 21, 2021
DVCon China 2021 at Shanghai China - May 26, 2021
CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021
True Circuits PHY



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise