June 28, 2004
Mini DAC Review + ESL Chapter 2
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

"2003 was a significant year because we finally saw growth in ESL," said Daya Nadamuni, principal analyst at Gartner Dataquest. "We believe ESL will be a primary driver of growth for the EDA market for the next several years."

According to Gary Smith there were 100 designs in 2003 using SystemC. Gary has been an evangelist for ESL for years.

At DAC there were several panel sessions related to ESL - North American SystemC User Group; System-Level Design 2004: Here and Now Technical Symposium; ESL: Fueling the Future of Submicron Silicon; and ESL Design: Your Future May Depend on It!.

I must confess that I overheard a conversation during which the speaker said she had successfully fought off an attempt to cancel one of these panels by someone who felt that a lot had been said about ESL but little had been accomplished. In the abstract for a panel discussion entitled “System Level Design: Six Success Stories in Search of an Industry”, the authors make the observation:

“System-level design is being touted as the Holy Grail that the electronics industry has long sought, but most offers have been disappointing because they seldom deliver results. Many designers are fed up with the “Blah, Blah” on system-level design as they are waiting for design facts.”

There is general agreement that the increasing complexity of designs is stretching the limits of existing tools and that a move to a higher level of abstraction would/should help address these challenges. The questions is whether any existing tool provides acceptable Quality of Results or perhaps better stated whether any existing tool provides QoR comparable to traditional approaches.

The authors observed that interest in ESL seems to be greatest in Japan driven by the convergence of computing, multimedia and wireless communications in single consumer electronic devices. By contrast designs in North America have been more component based than system based with the computing industry being the one to drive the design practices.

The authors noted that System Level Design does not share a common “design ideology”, as do digital designs from RTL to GDSII and is therefore closely associated with particular designs. This coupled with the small size of architectural and system design teams leads them to ask whether the most important ESL tools will be created and used within large system and semiconductor companies such as the ones represented on the panel, e.g. Intel and IBM. They further see a possibility for commercial IP industry to invest in the creation, proliferation and support of SLD tools tied closely to their offerings.

In preparing my first ESL article I interviewed Jeff Jussel, VP of Marketing fro Celoxica. As it worked out the material related to his firm fell on the editing floor to use a movie analogy. At DAC I had the opportunity once again to speak with Jeff and with Phil Bishop, the company CEO. Both had previously held executive positions at Mentor Graphics in the professional services division. The company was founded in 1996 using technology from the University of Oxford. Celoxica's headquarters are located in Abingdon, UK with major offices in Campbell, California and Yokohama, Japan. The firm employs around 60 people, has sold over 340 commercial licenses and has revenues approaching $10 million. The firm had a 70% growth rate year over year. On June 7th Celoxica announced $6 million of additional capital from existing investors.

Celoxica supplies the design technology, IP and services that define Software-Compiled System Design (SCSD), a methodology that exploits higher levels of design abstraction to improve silicon design productivity. Celoxica's products address hardware/software partitioning, co-verification and C-based synthesis to reconfigurable hardware.

In the Celoxica methodology, the designer integrates C-based models and explores algorithms and alternative architectures. Partitioning determines the optimal mix of hardware and software and functional verification is proven in cycle-based simulation. Designers can easily move design functions between hardware and software implementations using the Celoxica Data Streaming Manager (DSM) API. Applications can be quickly partitioned, profiled and repartitioned to find the optimal architecture for design performance. As in other systems there is no auto-magic hardware/software partitioning but rather a quick way to identify and evaluate. Software-compiled system design establishes direct implementation paths for both hardware and software functionality. The designer implements the system using a software compilation approach. Software portions of the design are compiled to object code, and hardware portions of the design are compiled directly to FPGA hardware.

The Celoxica DK Design Suite of system design tools, first released to production in March 2001, is now in its third major release.
Figure 2 Celoxica Design Flow

Jeff Jessel believes as do many of the others involved with ESL that designers and their managers are reluctant to move to a higher level of abstraction. While these people might concede considerable productivity gains and hence shorter TTM, they question the performance of design resulting from an ESL based flow. They feel that that can achieve optimum performance only at the RTL level. Of course the same sentiment was vigorously expressed when HDL was introduced as an alternative to schematic design. This is somewhat akin to software programmers who once felt that high level programming languages could not obtain the same raw speed as assembly language. The response to this concern is to show Quality of Results obtain in real world designs.

On the Celoxica website there is an on-line demo that walks through a design example from specification to FPGA implementation of an image processing system based on a JPEG2000 algorithm showing the Software-Compiled System Design methodology.

On May 24th Mentor Graphics announced its Catapult C Synthesis product that uses pure, untimed C++ to create quality RTL descriptions up to 20 times faster than traditional manual methods. This tool targets hardware designers developing ASICs or FPGAs for compute-intensive applications such as wireless communication, satellite communication and video/image processing. Depending upon one's definition of ESL, Capapult C may fall in or out of the category. It does raise the abstraction level and leverages the same untimed C++ source typically generated by system designers.

Catpult C is based upon ten years of internal development. This second generation high level synthesis offering has 9 granted or pending patents and has already produced 10 tapeouts. By uniting system-level and hardware design, the Catapult C Synthesis tool combines with the ModelSim simulator to create the central foundation for a C-based design flow.

The Catapult C Synthesis tool uses the accompanying Catapult C Library Builder tool to collect detailed characterization data from the downstream RTL synthesis tools with specific target technology libraries. This allows the tool to precisely schedule hardware resources, and quickly provide accurate area, latency and throughput estimates without spending costly time and effort going through RTL synthesis.

The Catapult C Synthesis tool environment ranges from $89,000-$275,000 and is available immediately on both one-year term and perpetual licenses.

I spoke with Shawn McCloud, Porduct Manager for Catapult C, about the advantages of his products. He said: “Untimed C++ is pure ANSI C++ which uses a C++ class library to model bit widths (ie: SystemC data types). Timed C++ embeds timing and hardware details in the source causing the source to be more difficult to write, have more lines of code, be locked to the interface, and be partially locked to the hardware technology. This makes the notion of micro-architecture and interface "what if" analysis impractical since it requires the user to spend time modifying the C source for each analysis.

Using pure, untimed C++, Catapult C Synthesis can perform the "what if" analysis by simply applying a new constraint through the user interface. The result is a source focusd on only functionality and a separate constraint file which specifies the hardware details. This makes design reuse far easier because to go from one technology to another means just changing the constraint versus changing the source.”

Letter to the Editor

Horgan and Henke's EDA market analysis would be more useful to me if it included a breakdown to the PCB Layout market level and if it included the Zuken results. While perhaps not an EDA Association member, Zuken results are available from the Japanese Stock Market.

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To read more news, click here.

-- Jack Horgan, EDACafe.com Contributing Editor.


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