February 16, 2004
Getting More than You Pay For - Part I
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


SofTech, Inc. and Cimmetry Systems announced a partnership. SofTech is licensing Cimmetry's AutoVue visualization and collaboration technology for its ProductCenter PLM (product lifecycle management) solution. The companies say, “Integration of AutoVue technology with ProductCenter PLM will extend the collaboration capabilities of ProductCenter, enhancing the solution's document management, design integration, configuration control, change management, and enterprise integration capabilities for optimizing product development.”

Synopsys, Inc. announced that the new release of PrimeTime has “set a new performance standard for static timing analysis and sign-off of 90-nanometer designs, enabling timing analysis of 100-million gate designs. Customer benchmarks show an average of 3x runtime improvement and up to a 3x data capacity improvement over the previous release.” Synopsys says the improvements are due to algorithmic improvements in reporting and static timing analysis, combined with a new save-and-restore capability that enables concurrent timing analysis of large, complex designs.

Also from Synopsys - The company, in conjunction with TSMC, announced that TSMC's libraries will now be distributed through Synopsys' DesignWare Library. The companies say, “the collaboration provides the more than 25,000 DesignWare Library users, at no additional cost, access to standard cell and I/O libraries created by TSMC and optimized for the company's 0.15-, 0.13-micron and 90-nanometer Nexsys Technology for SoC foundry processes. Synopsys will also offer TSMC's memory libraries for an additional fee. This agreement is the latest collaboration in a long-term relationship between the two companies. The agreement provides that both companies will optimize TSMC's standard cell and I/O libraries and produce design flows that deliver higher productivity and design quality to users.”

Following the announcement, I spoke by phone with Phil Dworsky, Director of Marketing for DesignWare IP at Synopsys. He said, “This is certainly a collaboration between two leaders acting on our customers' drive to bring more IP to them through a trusted IP channel, the DesignWare library. Our aim is to jointly lower our customers' risk and increase their time to volume. The process involves creating and validating flows, together with the silicon library and process, and will deliver standard cells and I/O libraries to our customers free of charge. We're going to give away the TSMC library, not that we won't make money in the equation. In fact, everybody stands to benefit and the [strategy] is well within our business model.”

I also spoke on the same phone call with Andrew Moore, Deputy Director of Service Product Marketing at TSMC. He told me, “We've worked together for a year. Our hand-off from designers is GDS. Now they will have a full set of tools to check that layout. More recently, we've been working with Synopsys on the TSMC reference flow, which includes most of the tools in the Synopsys platform. We've been making these libraries all along. Now we're giving them to Synopsys and asking them to give us any 'gotchas' back. This announcement with Synopsys cements our technical and business relationships with the company.”

Target Compiler Technologies NV announced that its Chess/Checkers retargetable tool-flow has enabled Gennum Corp. to accelerate the design of its newly developed 'Yukon' ultra low power microprocessor core, optimized for use in hearing instrument products. The Yukon core is the embedded controller used in an audio processing system already shipping in volume. Gennum says it used the Chess/Checkers tool-suite to develop a new, highly optimized application specific DSP core as a key component of a new multi-processor open platform. The new processor is currently made available to Gennum's customers on an FPGA prototyping board and will be in production later this year.

Don Shaver, Director of Product Development at Gennum, is quoted: “We wanted to design the best-in-class performance microprocessor and DSP cores for our specific type of application. Our aggressive schedules required us to perform simultaneous validation of the hardware and our application software. The maturity of Target's retargetable C compilation technology and the automated path to hardware generation that they offer were compelling reasons to select the Chess/Checkers tool-suite.”

Compiler Technologies was a spin-off from IMEC in 1996 and supplies retargetable tool suites for designing and programming flexible IP cores.

TransEDA and Verisity Ltd. jointly announced the availability of a flow in which TransEDA's Reqtify specification coverage technology is interfaced to Verisity's vManager verification management solution, linking design specification requirements to verification. The companies say the link between Reqtify and vManager brings the same best practices used by engineers in the automobile, aeronautics and defense industries to the semiconductor industry.

Per the Press Release: “Development teams need to ensure that all specification requirements have been verified in the final design. With today's systems becoming more complex, the need for requirements traceability and impact analysis during the design phase becomes crucial in order to enable quality development in SoC design. The interface between TransEDA's Reqtify and Verisity's vManager allows designers to boost the quality and time-to-market of SoC designs. Designers can verify that the design meets the initial specifications and replies to the needs of the customers.”

TSMC and Cadence Design Systems, Inc. announced efforts to create an integrated design capability that accelerates customers' time-to-volume for nanometer design. The companies say that as a result, Cadence becomes the first full-line distributor of TSMC's internally developed standard-cell and I/O libraries, and memories. In addition, the two companies announced they will collaborate to integrate TSMC's 0.15-micron, 0.13-micron and Nexsys 90-nanometer standard cell, I/O libraries and memories with the Cadence Encounter design flow, which was qualified to be included as part of the TSMC Reference Flow. The companies also say these developments are supported by the Cadence Design Foundry design services organization as well, which is a member of TSMC's Design Service Alliance.

Verific Design Automation announced that its products now support Accellera's property specification language (PSL)/Sugar - all of its HDL component software packages now include a PSL/Sugar reader and will, therefore, enable assertion-based verification. Additionally, Verific announced it has joined the PSL/Sugar Consortium. Harry Foster, the consortium's formal verification technical committee chair, is quoted: “The PSL/Sugar Consortium is pleased that Verific is offering assertion-based specifications within its HDL component software packages. This allows EDA companies to swiftly introduce native PSL/Sugar support in their verification tools. We were waiting for something like this to happen.”



Coming soon to a theater near you

DVCon 2004 - Organizers have announced the title for the keynote address due to be delivered by Cadence President and CEO Ray Bingham. The title of his talk is, "Making Design and Verification a Strategic Business Asset." The talk is set to showcase Bingham's vision for “taking the industry to the next level by providing valuable insight into the important role business transformation plays in the development and proliferation of technology and new products.” Right now, I don't really know what a business transformation is, but I hope to learn more at the talk.

2004 GSPx - The 2004 Global Signal Processing Expo and Conference, an embedded signal processing event, will take place from September 27th to the 30th at the Santa Clara Convention Center. Per the organizers, “GSPx provides opportunities for design engineers and developers to share their knowledge with an international audience of thousands of engineering colleagues. The expo brings together large companies from all over the world and is an opportunity to see, first-hand, the latest developments in state-of-the-art solutions, including design methodologies and processes, test and verification tools, and embedded applications. The expo keeps developers, engineers, designers, project managers, and executives abreast of recent advances and future demands.” The conference is co-sponsored by OCP-IP, Accellera, the Embedded Linux Consortium, SystemC, and the Rapid I/O Trade Association.



Newsmakers

EDAA Lifetime Achievement Award - The European Design and Automation Association announced that the winner of this year's EDAA lifetime achievement award is Prof. Hugo de Man. Prof. De Man works at the Catholic University of Leuven, Belgium. He also worked at the Interuniversitair Micro-Electronica Centrum (IMEC) in the same city, where he was one of the Vice-Presidents.

The award will be presented on February 17th during the keynote session at DATE 2004. EDAA says its decision reflects De Man's scientific achievements as well as his impact in industry. His many scientific achievements include the modeling of semiconductors, the design of analog, mixed-mode and digital simulators, research on the specification, verification and synthesis of telecommunication-oriented system design, contributions towards the design of asynchronous circuits, and novel system-level optimization techniques.

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-- Peggy Aycinena, EDACafe.com Contributing Editor.




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