February 09, 2004
From Glum to Glittering
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jeff Garrison, Director of FPGA Products at Synplicity, is quoted as well: “Synplicity and Altera have worked closely over the past year to provide superior support for Altera's new Stratix II device family. Our market-leading synthesis products perform special optimizations to take advantage of new features in Stratix II devices like the complex digital signal processing and memory blocks. We are excited to join Altera in servicing new market segments interested in these powerful new FPGAs.”
Ansoft Corp. announced a design flow using Ansoft's 3D electromagnetic tools for modeling and optimizing high-performance electronic designs that employ Xilinx Virtex-II Pro FPGAs. Per the Press Release: “FPGA platform solutions with high bandwidth DSP and Gigahertz-speed I/O place significant demands on PCB design. With the collaboration, Xilinx and Ansoft's joint customers can achieve multi-Gigabit speeds in their designs while using widely available, low-cost materials, connectors and PCBs.”
Suresh Subramaniam, Senior Design Engineer at Xilinx, is quoted: “In high-speed PCB design, it's astonishing how much extra performance you can obtain from off-the-shelf components when you optimize them with [Ansoft's] HFSS. With high-speed digital and analog RF components becoming more common in high-performance Xilinx PCB designs, using HFSS is necessary to assure the correct performance of the end design.”
Atrenta Inc. announced that Toshiba Corp. Semiconductor Co. has selected Atrenta's SpyGlass Predictive Analyzer to “enforce design reuse because of its broad and deep range of RTL analysis functions, rich customization capabilities, the ability to easily deploy the industry's best design practices and reuse guidelines, and the most comprehensive support for the STARC rules. STARC (Semiconductor Technology Academic Research Center) is a consortium of eleven major Japanese semiconductor companies including Toshiba that has defined a set of guidelines for SoC and ASIC design and IP, which are emerging as the de-facto standard in Japan.”
Seiichi Nishio, Senior Manager for Methodology at Toshiba, is also quoted: “After careful and rigorous analysis of all available options, including all existing tools currently in use, we found SpyGlass to be the superior choice because it fully met all our requirements - powerful underlying technology, full support for STARC rules including mixed-language support, ability to easily customize rules using C and Perl, and the capability to effectively incorporate and deploy our own design rules.”
eInfochips Inc. announced that it has increased its use of Verisity's Verification Process Automation (VPA) tools. eInfochips says it was one of the earliest companies to “actively embrace” Verisity's eRM (e Reuse Methodology) and Coverage-Driven Verification (CDV) methodologies and is “one of the strongest advocates of e-based verification.”
Mentor Graphics Corp. announced it is providing Intel Corp. with drop-in core layout (DCL) kits for use with Mentor's Expedition PCB design flow for Intel's next-generation chipset, code-named Grantsdale. The companies say that the DCL kit will be available through Intel and will provide an Intel reference motherboard design, which integrates the CPU, chipset, and other motherboard components for use with the Expedition PCB design flow. The companies also announced that the DCL kit for Expedition will be available this year following the introduction of the new chipset by Intel.
Per the Press Release: “As microprocessor speeds continue to increase, it is becoming more complex to meet interconnect timing and signal integrity constraints while placing and routing the critical components, while also minimizing the number of layers and overall size of the PCB. Intel is addressing this challenge by providing a reference motherboard design in Mentor's Expedition design solution to its customers.”
Nassda Corp. announced that Aeluros, Inc. has adopted Nassda's HSIM hierarchical circuit simulator and analysis tool for verification of physical layer integrated circuits for the 10 Gigabit networking and storage marketplaces. Don Stark, Vice President of Engineering at Aeluros, is quoted in the Press Release: “We were looking for a solution that would allow us to simulate our sensitive clock and data recovery (CDR) circuits together with the large synthesized logic blocks that they drive. These simulations would have been prohibitively slow with SPICE, but the speed and accuracy of HSIM allowed us to verify our entire CDR system at once, ensuring that it met our power and speed goals.”
Prosilog SA announced the availability of the release 2.0 of its Magillem tool, the graphical generator of SoC platform. The company says that Magillem allows “an easy interconnection between different IP's with the AMBA, CoreConnect, VCI and OCP protocols. The IP Creator module generates an OCP or VCI wrapper which facilitates the interconnect of the IP to the targeted bus. The code generated for the complete system is VHDL, Verilog or SystemC. Moreover, as a native XML-based platform, Magillem is following the recommendations from the SPIRIT consortium. The Magillem 2.0 release is particularly important for System designers who want to build a complete transactional platform in SystemC at different levels of abstraction, and mix HDL and SystemC IP's. The verification challenges are also addressed with the availability of the eVC (e Virtual Component) OCP2.0 module.”
RF Engines Ltd. (RFEL) has leased a hardware/software demonstrator to one of the French Atomic Energy Commission Laboratories (Commissariat a l'Energie Atomique or CEA) in order to evaluate the PFT (Pipelined Frequency Transform) signal processing hardware architecture, in connection with their ongoing program of real time RF signal characterization.
Per the Press Release: “The work was carried out at a CEA facility just south of Paris. The main purpose of the work was to benchmark the use of the Pipelined Frequency Transform (PFT), one of RF Engines proprietary FPGA signal processing designs, for the analysis of very short duration incoming RF signals. The work focussed on pulse width measurement performance of the PFT, and assessed the performance of signal detection, acquisition, and tracking of signals down to 100-ns width, across a matrix of tracking speeds and durations. The RFEL development system used for the work incorporates a scaleable PFT with up to 1024 points running on four 1 million gate Xilinx Virtex E FPGAs, with performance data being displayed via RFELs proprietary software ASDS (Advanced Spectrum Display Software).”
Silicon Dimensions Inc. announced a new product, Chip2Nite, which the company describes as “a suite of tools that enables comprehensive design planning and analysis of complex hierarchical integrated circuits. For the first time, design teams have a platform that will enable logic designers and physical designers to use their combined expertise to rapidly complete block designs - resulting in reduced cost, lower risk and improved time to market. The Chip2Nite products directly address the difficulties encountered in current methodologies by enabling logic design engineers to contribute to design closure early in the development process. The wire centric technologies used throughout the product suite enable logic designers to rapidly model the resulting physical design. The use of multiple "what if" scenarios and analysis, for the first time, makes it possible for logic designers to produce designs that are near optimal for physical design closure.”
Rita Glover, EDA Industry Analyst and Consultant for EDA Today, is quoted in the Press Release: “Silicon Dimensions addresses one of the EDA market spaces where we see growth in 2004. With design starts at 130 nanometers and below rapidly increasing, design planning is becoming essential to avoiding design closure delays and development expense. Logic designers need to have tools that enable them to understand physical constraints to design efficiently and partner with the physical designer in the final closure process.”
Synopsys, Inc. announced that Toshiba Semiconductor Co. has licensed the rights, on a per-use basis, to use Synopsys' alternating phase-shift mask (PSM) technology for production of high-performance processors and logic chips. Toshiba says it expects to enter volume production at 65-nanometers using this technology in the first half of 2005. Per the Press Release: “In December 2002, Toshiba developed the CMOS5 65-nanometer production process technology, which offered 30-nanometer transistors and 180-nanometer pitches using 193-nanometer argon fluoride (ArF) lithography and PSM technology.”
Masakazu Kakumu, Technology Executive for Toshiba, is also quoted: “Our research and development qualification shows that Synopsys PSM technology enables us to increase our yields and control our chip performance at 65 nanometers by substantially improving the resolution of our existing lithography equipment. Having strong control over our lithography process is a critical component in meeting our yield goals for production on this difficult node.”
Triad Semiconductor Inc. announced it has purchased ViASIC Inc.'s ViaPATH software to design custom ICs that require only a single mask layer change for fabrication. Triad Semiconductor says it plans to fabricate the first chip using ViaPATH in Q1 2004.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.
Be the first to review this article