February 02, 2004
High Priests & Gurus
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Meanwhile, all of them talked about the new Agilent simulation model for high-frequency GaAs and InP heterojunction bioplor transistors (III-V HBTs). (Better go journal hunting again, because this new model was just announced as an Agilent product in the December 2003 issue of Microwave Journal, “A Nonlinear Circuit Simulation Model for GaAs and InP Heterojunction Bipolar Transistors.”)

I don't know about you, but I'm exhausted - all of this and we still haven't even gotten to the actual interview, the part where Root and Iwamoto tell us in their own words what all they've been doing lately in the in Santa Rosa labs. So here it is, at last. The high priests speak ...

In their own words

David: There's a technical subset of bipolar junction transistors called III-V heterojunction bipolar transistors (III-V HBTs). The III-V means they're transistors made from semiconductor compounds involving atoms from group III and group V of the periodic table. Examples include bipolar transistors made up of GaAs and InP [as opposed to doped-up 'pure' silicon transistors, or SiGe (a IV-IV HBT), which always get a lot of press]. Heterojunction refers to the fact that the transistors are made from junctions of different materials, such as InGaP/GaAs and InGaAs/InP. These extra degrees of freedom (band-gap engineering) enable the design of state-of-the-art high-performance transistors.

The market for GaAs and InP HBTs is not the same as the market for Si-based BJTs. GaAs and InP HBTs are important today because of specific advancements being made for specific applications, such as power amplifiers for handset phones and wireless LANs (GaAs HBTs), and high data rate communication applications (InP HBTs). One of the important issues is how to design products for these markets using these different devices - III-V HBTs versus more common homojunction BJTs. A necessary tool for designs in these technologies is a nonlinear circuit simulation model for III-V HBT devices - which is what Masaya and I have been working on. We've developed a new comprehensive nonlinear III-V HBT model, which was announced last December.

Masaya: This model is specifically formulated for III-V HBTs, namely for GaAs and InP HBTs. There has been a lot of previous work on this, but one of the key contributions of this model is the comprehensive nonlinear transit time model, important at high frequencies, that has been shown to be related to distortion. We're able to get a better prediction of linearity with this nonlinear transistor model.

David: This model is the first to integrate the specific physics of the III-V HBT in a mathematically consistent way and the first to be incorporated in robust production code for a wide variety of heterojunction devices.

Masaya: I started working on this technology when I went to graduate school. I wanted to study HBTs, which is why I went to UCSD. I was aware at the time that Agilent was doing work with GaAs. So basically, during the summers at UCSD, I interned in Santa Rosa. My principal work was in HBT modeling and characterization and that was the work that led to this HBT model. After I finished, I was hired full time and have been here in Santa Rosa for just over a year now. I'm working with David on the III-V HBT model and also involved with HBT process development.

David: Masaya and I have developed this model at the Agilent Worldwide Process and Technology Center, and now we're working with the EEsof EDA Division to implement a robust version that can be integrated with their design tools.

Joe: The labs and the EEsof Division are adjacent to each other here in Santa Rosa.

David: In the process of working with EEsof, we've had the opportunity to work with design houses and foundries to extract our models. In particular, we worked with WJ Communications [the commercial products descendent of Watkins-Johnson] over a year ago to validate the early work. Based on such validations, and those conducted on our own internal Agilent devices, we now have a very accurate robust general model for the III-V HBT device that provides a significant advantage for those circuit designers who are working in high-speed analog circuit design.

Part of our motivation for this work is that III-V HBT devices have different characteristics than silicon BJT devices. The velocity of the charge carriers in III-V HBTs, as a function of the electric field, has a different shape compared to that found in Si BJT devices. That microscopic physical property directly translates into different device level characteristics - the speed of the device, as a function of the applied voltage, for example, has a different shape, which affects how the devices perform in circuits in several ways. So to design in these new III-V heterojunction bipolar processes that behave differently than more traditional processes, it's important to have accurate nonlinear models of the behavior.

In our labs in Santa Rosa, our colleagues have developed semiconductor processes in these compound materials using a wide variety of techniques. We do FETs (MESFETs and pHEMTs) in GaAs, and now III-V HBTs in GaAs and InP. We're also developing high-speed broadband ICs from these technologies at our facility. They have been for our internal proprietary use within Agilent for the Test and Measurement Business.

Masaya and I work “between” the semiconductor fabrication engineers and the circuit designers. It's our job to help characterize, analyze, and model the behavior of the devices we produce for the products we design, as well as feed back information to improve the semiconductor design process. This direct experience with novel in-house semiconductor processes and cutting edge circuit designs is directly responsible for the successful modeling efforts.

Now, we're working with the EEsof Division to provide this model to our customers. The collaboration is an interdisciplinary one - device physicists, material scientists, characterization engineers, circuit designers, and the first-rate tool design engineers from EEsof, make up our team now providing these tools to external customers.

As we've had these models underway internally for a long time, we're technical pioneers ourselves on behalf of internal users. But to get our models adopted for use by our larger user community, we've needed to make an additional effort. Masaya and I have published many of the details of the equations and the formulations. This is necessary to have the model principles of operation understood, a prerequisite for adoption by the wider community. However much of the key IP in the model is in the implementation details - the implementation is proprietary.

Meanwhile, if we can convince people of the material and physical robustness of the work with data from independent non-linear experiments, we will have better success in incorporating our models into the mainstream tools. That will provide benefit to Agilent customers, as EEsof is able to commercialize the models.

Joe: One of the issues around commercialization is for a business division to be convinced by R&D that there's a market for what's been developed. From our perspective, before a big market is necessarily recognized, we can observe collaborations that result from work to meet internal needs. The subsequent efforts to develop and prototype models for commercialization is a process that depends on who the players are and where the technology is going. Our implementation engineers work closely with the R&D team through a carefully planned project to do this, but the real research and prototyping phase has already been done for internal users.

David: Part of the effort is getting a commitment from other business divisions to commercialize our work and then to start working together to define the project and have Marketing ratify it. Then, of course, it's the process of getting the resources to take an internal project and make it into an external project. In the case of the new HBT model, while this process was going on, we were still developing the prototype. We did some customer pre-qualifications of the model based on the perception that we needed to see a real customer at their own foundry to test the model.

Over a year ago, we were able to work with an external foundry and have Masaya extract the new model with respect to their model. We were able to provide an early prototype of our model, which was the feedback that EEsof needed to convince them that the model worked and that there could be an application for a wide variety of customers. We had already done extensive validation of the model with respect to our internally developed devices. It was somewhat annoying that we had another hurdle to jump before commercialization was approved. However, things are certainly moving in the right direction now. Besides, we almost always learn new things from talking with other customers about their needs and problems.

« Previous Page 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.

Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
More Editorial  
Latest Blog Posts
Modesto (Mo) CasasGlobal Business in EDA
by Modesto (Mo) Casas
The Contingent Purchase Order Reassures Buyer and Seller
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Meet the New Cylynt, Fighting Software Piracy Around the Globe
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Physical Design/Layout Engineer for EDA Careers at EAST COAST, California
Digital Design ASIC Manager for EDA Careers at RTP, North Carolina
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Upcoming Events
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise