Genda Hu, Vice President of Corporate Marketing for TSMC, is quoted in the Press Release: “Our collaboration with Cadence to verify Fire & Ice QXC allows mutual customers to take full advantage of TSMC's leading-edge process technologies.”

Denali Software announced that Unisys Corp. has licensed Denali's PCI Express verification tools for the development of the PCI Express interfaces in the Unisys ES7000 server chips. Unisys says its engineers are using Denali's PureSpec verification IP to model, simulate, and verify the interface between Unisys chips and other PCI Express compliant devices, and that by using PureSpec, Unisys engineers can expose potential interoperability bugs early on in the development cycle before the designs are implemented in silicon.

Diep Nguyen, Hardware Engineer Manager at Unisys, is quoted in the Press Release: “Denali continues to be a key innovator with tools and technology for interface modeling and interoperability verification. Using Denali's PureSpec helps us verify that our designs are compliant with the PCI Express standard and interoperable with other PCI Express implementations.”

MIPS Technologies, Inc. announced that it is pleased that its “long-time partner” Toshiba has formed a strategic alliance with DENSO Corp. of Japan to develop car navigational devices for the automotive market.

Per the Press Release: “Designers of automotive applications, such as navigation and infotainment products, are driven by the often conflicting demands of offering a rich car user experience while keeping costs down and getting to market quickly … The strategic partnership between Toshiba and Denso includes co-development and implementation of a multi-operating system (OS) platform that forms the basis for advanced SoC designs by enabling uITRON (the predominant embedded operating system for deeply embedded devices targeted for the Japanese market) and Windows Automotive in a single OS environment. This multi-OS environment will utilize the high-performance MIPS architecture to enable user applications, such as Internet and network connectivity and the display of audio and video content.”

Also from MIPS - The company announced that Genesis Microchip has taken a license for the MIPS32 4KEc core for use in its digital TV applications. Anders Frisk, Executive Vice President of Genesis, is quoted in the Press Release: “The 4KEc core from MIPS Technologies offers a high-performance applications processor that matches the overall system performance of our digital TV processors.”

ProDesign announced the CHIPit Silver Edition, which the company describes as “the newest member of the CHIPit family” - a rapid prototyping and IP verification platform that ProDesign says is designed for use in PCs and workstations.

Per the Press Release: “The platform distinguishes itself through use of a VIRTEX-II FPGA from Xilinx, as well as with excellent memory resources and possibilities for expansion. The CHIPit Silver Edition communicates with its host, as do all products of the CHIPit range, via the ProDesign proprietary UMRBus Communication System. Using this technology, multiple independent communication channels between the host and a design can be set up, whilst the handling remains simple and intuitive. The CHIPit Silver Edition is particularly suited for co-emulation verification of IP cores, ASIC designs, or parts thereof - the optional HDL-Bridge package provides interfaces for the HDL simulators ModelSim and NCSIM. This package includes a tool for implementation of multiple IPs in hardware, which also gives the possibility of simultaneously spreading multiple IPs across multiple CHIPit Silver Edition platforms. As programming interfaces, the user has the choice between C/C++ and Tclk/Tk.”

Silicon Canvas Inc. announced its LakerT1 product, which the company says is a platform for Process Test Chip Development (PTD). Per the Press Release: “Laker T1 is the first commercial product of its kind. It can be used by pure foundry houses and IDM companies to calibrate and qualify IC process technologies. It can be also used by cutting-edge fabless houses, which have special devices of their own kind. Based on its relationships with the world's leading foundries such as TSMC, Silicon Canvas developed Laker T1 to enhance and streamline the conventional PTD flow. With Laker T1, cycles that usually took two years and three-to-six re-spins in the conventional flow can be shortened to eight months or less, and with only zero or one re-spin. Clients using T1 can realize a huge ROI from equipment depreciation alone, let alone other intangible benefits such as better yield, early time-to-market gains, and more flexible business models.”

“The PTD cycle is quickly becoming one of the leading barriers to market success for pure foundries houses and IDM companies. Escalating development costs combined with longer development lead times prohibit many fabs from placing complete and thoroughly scrutinized test structures and test lines into the test chips. The problem continues to feed on itself as the lack of critical correlation and test data makes their way though the PTD cycle.”

“For example, a 300mm wafer fab costs between $2B and $4B to build. Typical mask costs range from $750K for 130 nanometers to $3M for 65 nanometers. The conventional PTD models, most of which are created by trial-and-error, can take as long as 2 years to complete and require 3-to-6 correction spins - a methodology that obviously is no longer cost effective.”

“Designers who are using the services of a fab require a Process Test Chip Development approach that can reduce the re-spins and shorten the overall PTD cycle, while providing a systematic way to generate sufficient and meaningful data required to qualify a fab. With Laker T1's systematic reusable and scalable approach, foundries can easily create multitudes of test structures and test lines targeted at providing detailed coverage of the many different aspects of PTD. This will aid in obtaining faster convergence between the process' electrical performance and equipment resolution. In turn, the foundry can deliver a more comprehensive specification to the customer with overall increased confidence in design for manufacturability. The bottom line is a faster ramp-up time.”

Synopsys, Inc. announced Taurus Process Atomistic, which the company describes as “a new process simulation tool for sub-90-nanometer semiconductor device manufacturing … which accelerates the development of semiconductor processes and improves yield.” Synopsys says that Taurus Process Atomistic offers up to 40-percent faster/more accurate simulation of nanoscale semiconductor device structures.

Per the Press Release: “As semiconductor manufacturing scales below the 90-nm node, the tools needed to model and simulate process technology and behavior must consider physics effects that are significantly more complicated than previous generations. Taurus Process Atomistic performs a simulation of the diffusion of atoms within a transistor, which determines the transistor's ability to carry electrical current. In addition to enabling successful process development, the precise simulation of these effects is critical to the ability to characterize transistor power and performance.”

Don MacMillen, Vice President of Engineering in Synopsys' New Ventures Business Unit, is quoted in the Press Release: “By improving the ability to accurately model advanced processes, we are improving our customers' ability to develop chips that will meet yield and performance expectations. Taurus Process Atomistic offers a unique combination of accuracy, simulation speed and integration. Because the number of atoms in each transistor goes down with feature size, atomistic simulation times decrease with each process generation, offering a speed improvement of orders of magnitude over traditional techniques. Taurus Process Atomistic is used by process technology integration teams to more accurately predict certain characteristics and variations of ultra-shallow junctions that impact transistor performance and leakage.”

TriCN and Tower Semiconductor announced an agreement under which TriCN will provide its Base I/O library and a suite of high-performance interface IP to Tower for use in their 0.18-micron process. Tower says it will make this IP available to customers designing high-performance chips for production at Tower's Fab 2 facility.

Sergio Kusevitzky, Vice President of IP and Design Services with Tower Semiconductor, is quoted in the Press Release: “We're standardizing on TriCN technology for our interface IP needs because of their distinguished track record developing high-performance interfaces. Furthermore, the flexibility of their Base I/O library allows customers with a wide range of design applications to successfully develop chips with minimal risk. We believe this is a key benefit for customers designing next-generation ICs for production in our fab.”

The X Initiative announced that UMC is the first pure-play foundry to become a member of the semiconductor supply-chain consortium. UMC says it is now ready to accept X Architecture designs for fabrication at the 180-nanometer, 150-nanometer, and 130-nanometer process nodes. Per the Press Release: “The availability of production fabrication for X Architecture designs is a critical step toward broad commercial adoption of this new chip-wiring architecture. The X Architecture represents a new way of orienting a chip's microscopic interconnecting wires using diagonal pathways, as well as the traditional right angle, or 'Manhattan,' configuration. By enabling designs with significantly less wire and fewer vias (the connectors between wiring layers), the X Architecture can provide significant, simultaneous improvements in chip performance, power consumption and cost.”



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-- Peggy Aycinena, EDACafe.com Contributing Editor.