June 09, 2003
EDA, Inc.
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

“Software and firmware developers don't need low-level modelling of the hardware – they only need noughts ['Brit-speak' for zeroes] and ones to understand if their software is working.”  

“So I would put virtual silicon across a spectrum, which means that Gary and I are both right. There's virtual silicon at every level – for example at the instruction-set simulation level, at the cycle accurate modelling level, as well as the detailed electronic level.”

“The reason that everyone is talking about virtual silicon is the SoC. In the past, silicon was simpler and its functionality stood alone. But now, the point is that every chip is effectively an SoC and software is critical to the operation of the chip as a system.”

“Writing the software requires cycle-accurate models of the chip on which it will run. This 'virtual silicon' allows software development to begin as early as possible in the design process. In the past, such models were created by hand, with power users employing their own modelling teams in-house.”  

“Now, however, at 90 nanometers, the chips have 100 million gates. When your design has 100 million gates, you can hardly write a model by hand. Hence the emergence of specialist tools from vendors such as TenisonEDA to meet that need.”  

(Editor's Note: It's not clear how to distinguish between “silicon virtual prototyping” and “virtual silicon prototyping.” Are they one-in-the-same or distinctly different?)

Issues at DAC – Partnering and Power

Tuesday morning at DAC, I had a chance to converse with Ron Nikel, CTO of TriCN and Brani Buric, Senior Director of Product Market at Virage Logic in a jointly held briefing. The two companies are partnering in a serious way.

We started by discussing the partnering issues that had been mentioned in depth by ARM's Sir Robin Saxby in his keynote address earlier in the morning. Clearly the two companies agree about the need for partnering across corporate firewalls and this particular partnership seems to be benefiting both companies. Let Sir Robin extol the virtues of partnering. Let him explain how partnering requires trust and openness, contracts, confidentiality, and regular meetings to minimize miscues. These two companies, TriCN and Virage, are executing on the theory in tangible and constructive ways.

The results of the partnership has been the creation of a Base I/O library compatible with both the Virage semiconductor IP platform and TriCN's portfolio of high performance interface products – the I/O library is available for purchase from both companies.

Virage Logic's Buric said, "Partnerships have to be viable on both the business level and the technology level to make sense to the companies involved. And they can't just be a result of reactions to a perceived problem up ahead. Partnerships have to emerge as a result of producing real solutions to real world problems. Companies need to have common goals and a good perception of what makes sense from a business perspective."

TriCN's Nikel said, "We've admired Virage for a long time as an example of how to successfully grow an IP company. We've viewed their ability to dominate the memory space as a model for how we would like to dominate the I/O space. Given our synergistic product portfolios, working together made a lot of sense."

Ron Nikel went on to explain his take on the current crisis in power management in high-end designs: “'Power' seems to be the new buzzword here at DAC, as if this is a problem that has just emerged on the horizon with the latest geometries. But the potential concerns related to power have been evident for some time now.”

“Most people think that the main power issue at 130 nanometers is static power. In fact, dynamic power creates just as big a problem at both 130 and 90 nanometers, due to the increased power density caused by increases in transistor density and higher clock frequencies. A large amount of dynamic power can create huge issues with heat dissipation, and if it's dealt with ineffectively, it can result in huge packaging costs.”

“So power management is a worthy goal for any number of reasons. By reducing a chip's total DC requirements, the thermal characteristics are also reduced, which results in longer reliability for the product. You also increase the reliability of predictions, as higher dynamic power and behavior results in IR drops and timing that is out of line.”

“We are continually addressing power issues as they relate to high performance interface development. For example, in the area of multi-gigabit SerDes design, traditional analog design creates enormous demands for power consumption. We recognized this several years ago and developed an all-digital SerDes design that has significantly reduced power demands versus an analog alternative design.”

“As the industry moves to even smaller geometries – 90 nanometers and below – what types of companies are going to be first on the scene? The most likely ones are those who gain the most from small real estate and high performance, such as producers of WiFi or Bluetooth products. Of course, power conservation will be very high on their list of issues with which to contend.”

“Clearly, technology partnerships are going to become more important in dealing with the challenges brought on by those technology advancements. Given that smaller geometries will have longer turn-around times and higher mask costs, companies making the move to the next technology nodes will need to rely more and more on outsourced IP products to reduce time to market and risk.”

“The development of our Base I/O library is a good example of how we worked with partners – in this case, Virage Logic – to anticipate and help address customer issues, including power. We created this library because we recognized that existing libraries in the market required significant re-engineering to manage the demands of high performance design. The TriCN team consulted with Virage on the optimal way to address power, ground, and noise isolation issues, among others. The Base I/O library helps meet our customers' demands for performance as they increase, and is also a building block for a broader set of products that includes the Semiconductor IP Platform offered by Virage and the TriCN high performance interface IP portfolio.”

I think Sir Robin would be proud.

Issues at DAC – Italian Zest and the many flavors of SPICE

As compelling as Saxby's keynote was on Tuesday morning, Alberto Sangiovanni-Vincentelli's talk was even more so, as he wrapped up DAC 2003 with the closing keynote on Thursday afternoon.

It was a rollicking hour of history, philosophy, technology, economics, not to mention Italian sparkle and charm. Even if you weren't a technologist, you would have been caught up in Alberto's zest for life. If you were a technologist, you would have found his talk riveting – particularly if you're interested in how we got from there to here in EDA.

You should know that, thanks to the magic of modern computing and data storage, the ENTIRE 40 years of DAC proceedings is now available on a single DVD, and in fact, was included with the conference materials given out in Anaheim. Think about what this means. Think about 40 of those 20-pound tomes that have been gathering dust on your bookshelves. Think about the technology advances that have had to occur in order to achieve this level of information density. It is nothing short of spectacular. Mind-boggling, really.

Take that sense of wonder and whimsy, apply it to an IEEE fellow, long-standing faculty member of the EECS Department at U.C. Berkeley, and someone who helped to found both Synopsys and Cadence – and you'll see why, when Alberto accepted DAC Chair Ian Getreu's invitation to deliver a keynote summarizing the 40-years-of-DAC DVD, it was destined to be an unforgettable moment in the annals of DAC keynote speeches. After all, Alberto himself wrote a part of that 40-year EDA history.

More details later, but for now – let's just dwell on one piece of that history that was mentioned in Alberto's talk, something associated with U.C. Berkeley, as well. It's the workhorse of IC design, the SPICE simulator. Even before the keynote on Thursday, I happened to be in a meeting with Dima Smolyansky, Product Marketing Manager for TDA Systems, and got into a discussion about SPICE. I asked Dima why SPICE, which could be characterized as a fairly old technology, remains the lynchpin of signal integrity simulations even today?

Dima told me that it is important to TDA that they remain vendor neutral on this topic. Nonetheless he offered these comments: “The original SPICE, the Berkeley SPICE, is in fact an old technology. The commercial versions of SPICE, however, have evolved substantially. The simulation algorithms have been optimized to run faster and to intelligently select the simulation step and tolerance. Very powerful schematic capture tools have been developed, and large libraries of active and passive components now come with SPICE tools. Some SPICEs are capable of handling frequency dependent losses, and some even claim to be able to handle the frequency dependent S-parameters.”

« Previous Page 1 | 2 | 3 | 4 | 5 | 6  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.

Review Article Be the first to review this article

Hardware Engineer, Board Design for Arista Networks at Santa Clara, California
Salesforce Technical Lead   East Coast  for EDA Careers at Cherry Hill, New Jersey
Sr. Application Engineer for Mentor Graphics at Fremont, California
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Senior Software Architect Internet for EDA Careers at San Jose, California
Upcoming Events
FLEX 2020 and MSTC 2020 at DoubleTree by Hilton 2050 Gateway Place San Jose CA - Feb 24 - 27, 2020
DVCon U.S. 2020 at DoubleTree Hotel San Jose CA - Mar 2 - 5, 2020
OFC 2020 - The Optical Networking and Communication Conference & Exhibition at San Diego Convention Center San Diego CA - Mar 8 - 12, 2020
DATE '2020 at ALPEXPO Grenoble France - Mar 9 - 13, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise