Also from Magma Design - The company announced that WIS Technologies Inc. used Blast Fusion and Blast Rail to complete what the company calls single-pass design closure on a 5-million-gate, 100 MHz, 0.18-micron designs. Additionally, Magma said that WIS was able to tapeout the design in 2 weeks without iterations.

Nassda Corp. announced that Aeroflex Microelectronic Solutions has adopted Nassda's HSIM full-chip simulator and analysis tool for verification of memories and complex mixed-signal designs in Aeroflex's high-reliability IC families for the aerospace and defense markets. Aeroflex engineers have applied HSIM in pre-layout and post-layout verification of a 0.18-micron CMOS memory design, a 0.35-micron memory, and two 0.25-micron CMOS mixed-signal designs. The memory designs include a 128Kx32 rad-hard SRAM memory with 60 million transistors and a rad-hard 32Kx8 PROM with 600K transistors. The mixed-signal designs included a LVDS serializer and an LVDS deserializer, each containing a PLL.

Palmchip Corp. announced the availability of what the company describes as “the industry's first complete serial ATA IP solution.” The product includes the serial ATA target core, the host core, and the analog PHY developed by Astro Semiconductor (see Newsmakers). Palmchip says it announced its serial ATA host controller core and serial ATA target core earlier this year. Through a recent agreement with Astro Semiconductor, Palmchip will now provide the analog PHY IP.

Pulsic Ltd. announced the new release of its Lyric Physical Design Framework, which the company describes as a “next generation physical design tool suite that provides a flexible, high performance auto/interactive routing and ECO placement solution for all IC design types, including complex analog, custom, mixed-signal, and SoC designs.” the Lyric IC Router module has been enhanced to include improved features and performance in terms of speed and completion, and tools for routing DRAM and SRAM memory designs. New physical placement capabilities provide support for ECO, deep-submicron process rules, and support for 64-bit computer architectures.

Sagantec announced Anaconda, a schematic-driven, constraint-based compaction tool intended to accelerate analog physical design by automating repetitive manual layout tasks and allowing analog design reuse. Anaconda targets the manual effort involved in analog reuse today, correctly placing and sizing the layout details of the derivatives and variations of a given physical topology and the migration of circuits to new processes. Anaconda reads sizes and constraints from a schematic and then refines a given topology to automatically implement the specifications to produce a complete layout.

Sequence announced that NVIDIA Corp. used Sequence's PhysicalStudio in six successful tapeouts. The companies says that one of the tapeouts was the GeForce FX 5800 Ultra GPU, a chip which incorporates numerous “out-of-this-world features” such as real-time rendering, and that the project posed complexities and design challenges NVIDIA addressed with the Sequence tool. Additionally, Sequence announced that it is releasing the next-generation of PhysicalStudio, with new signal-integrity, power-optimization, and voltage-drop analysis features that the company says are tuned for 90-nanometer design. (More discussion to follow next week.)

Silicon Canvas, Inc. announced Laker 3.1, which the company describes as “the first connectivity-driven layout tool for controllable automated full custom design.” The company has incorporated its Controllable Automated Technology (CAT) and connectivity-driven layout methodology into the existing rule-driven Laker product. Laker 3.1 is intended to allow layout designers to reach “handcrafted” layout quality from the netlist or schematics in much less time than previously required, without undergoing the difficult process of manual full-custom layout. Additionally, the tool's ECO capability, stick diagram, cell template, and rule-driven technology permit different layout topologies to be explored and manually modified. Designers can maintain control over the quality of the layout, while the tool automatically performs much of the formerly manual process. The company says that measured productivity gains conservatively range from 2x to 6x on chips designs that vary from analog/mixed-signal ICs to SoCs.

Silicon Metrics announced that it has joined Synopsys' Milkyway Access Program (MAP-inSM). The company says it has tightened the integration of its SiliconSmart characterization products with the Synopsys Galaxy Design Platform for timing, power and signal integrity design closure, and this will result in better-performing nanometer design flows when used with tools in the Galaxy Design Platform.

Synopsys, Inc. announced a partnership with Airbus that has developed a new tool, Saber RT, for the simulation of systems in the Airbus A380 - described as the world's largest passenger airplane. The companies say the new tool allows for interactive simulation of many systems including hydraulic components, and that Airbus has used the tool to save prototype costs and speed time-to-production. The companies also say that traditionally, multiple hardware prototypes costing up to $10 million are needed to simulate the thousands of functions in large systems - everything from an overhead light to the landing gear. Synopsys says that Saber RT performs “interactive” simulation, which behaves identically to an actual hardware component and eliminates the need to build multiple components, while functioning as a bridge from simulation to production.

Also from Synopsys - The company announced that ATI Research, a subsidiary of ATI Technologies, Inc., has adopted Synopsys DFT Compiler SoCBIST to implement the design-for-test architecture for its upcoming visual processor. SoCBIST is an extension to DFT Compiler. By using SoCBIST, ATI says it is able to improve test quality and reduce test cost for ATI's visual processing unit with 200+ million transistors of digital logic. The companies says that a design of this size and complexity requires extremely high stuck-at fault coverage, and thorough testing for delay-related defects, the most common defect type in 0.13-micron process geometries and below.

Finally from Synopsys -The company announced Magellan, which a new hybrid formal verification product. The company says that Magellan combines advanced formal engines with the “strengths of the built-in VCS simulation engine to help engineers uncover bugs that may be buried thousands of cycles deep in the design.” The tool's hybrid architecture provides deterministic results that the company says are free of false-negative errors. Magellan supports Verilog and VHDL designs and is architected to work with the emerging SystemVerilog standard. It is part of the design-for-verification (DFV) strategy being pursued by Synopsys. The press release was accompanied by a testimonial from NVIDIA Corp. who said they used Magellan for developing NVIDIA graphics processing units.

Tanner EDA introduced the latest release of its layout and verification software, L-Edit Pro version 10. The software runs on Windows and is used for analog and mixed-signal IC, MEMS, and integrated optical device designs. New features include hierarchical DRC and the ability to utilize hierarchical information to eliminate redundant checking of duplicated geometry. The hierarchical error browser allows users to view and correct errors at the level where they occur in the hierarchy. L-Edit Pro 10 also provides all-angle DRC for MEMS and optical designs, and supports all-angle polygons and wires, circles, arcs, pie wedges and tori curve editing, layer generation and Boolean/grow operations, and improved dimension display and multi-language menu options (English, Japanese, Russian and German).

ViASIC Inc. announced a new one-mask modular array architecture and new physical design software for modular arrays, as well as a design kit that the company says includes everything a design team needs to implement a TSMC one-mask design, including the software, a technology license, and the master tile. ViaMask is a one-mask architecture for 0.18- and 0.13-micron foundry processes. ViaPath is a physical design tool for placement, optimizing, and routing a one-mask design, intended to reduce the number of custom masks required to configure logic from up to 28 masks to just one. The company says the new products will allow modular array technologies such as those from LSI Logic and NEC to reduce customized masks per design by 4x or more and will address the gap between FPGAs and the increasing cost and complexity of standard-cell ASICs.

Zenasis Technologies, Inc. announced ZenTime, the first product to use the company's hybrid optimization technology. The new tool is intended to help ASIC and SoC design teams reach target performance by injecting large timing gains into their designs in “just the right places.” ZenTime can generate timing gains using a hybrid of transistor, logic and physical optimizations that are 2x to 4x larger than conventional timing closure tools. The company says ZenTime can gain over 50 MHz in additional performance in 130-nanometer processes, The tool operates simultaneously at the transistor, gate, and physical levels, and the hybrid optimization combines “the benefits of custom-cell crafting, physical optimization, and placement accurate timing.” The company says that by optimizing at the transistor-level, ZenTime finds ways to improve timing using fewer or smaller transistors and fewer inter-cell wires, and therefore improves timing without introducing power, area, or signal-integrity penalties. The company adds that no change is required to existing synthesis or physical design tools when ZenTime is added to a flow.



You can find the full EDACafe.com event calendar here.

To read more news, click here.


-- Peggy Aycinena, EDACafe.com Contributing Editor.