August 19, 2002
EDA Week In Review
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Troubled HPL Technologies Inc. replaced Elie Antoun with Tom Tomasetti as chief executive, who most recently was at The Brenner Group, which specializes in placing experienced executives in interim jobs.
Tundra Semiconductor Corp. said that it has been appointed to the Steering Committee of the RapidIO Trade Association. The Steering Committee acts as the governing board of directors for the industry standards association. The Steering Committee oversees the management of the RapidIO Trade Association and determines the technical and marketing direction of RapidIO Technology on behalf of the membership at large. This committee is composed of leading system and semiconductor companies including, Alcatel, EMC, Ericsson, IBM, Lucent, Mercury Computers and Motorola. The RapidIO Trade Association was formed to address the need for a next-generation interconnect technology for the embedded networking and communications industry.
Axis Systems, Inc. announced its Assertion Processor, a new system-on-chip verification technology that the company said enables designers to accelerate and emulate assertions, which are used to verify chips. Assertion Processor accelerates assertion-based verification by 1000 times or more, and is expected to increase designers' confidence that design flaws will be found before a chip is manufactured, Axis also reported.
Assertion Processor will enable designers to incorporate assertions into their designs during acceleration and emulation, without requiring any changes to their existing verification methodology. Axis' entire product line has incorporated the new Assertion Processor, including Xtreme, Xtreme II, and Xcite. All of the Axis products are based on the company's patented ReConfigurable Computing (RCC) technology, which combines simulation, acceleration, and emulation on a single platform. (Assertions are statements that document a designer's assumptions and properties of the design.)
In related news, 0-In Design Automation and Axis Systems, Inc. announced a tool combination of assertion-based verification with hardware acceleration and emulation in order to increase verification productivity for large, complex IC designs. The 0-In/Axis assertion solution is meant to enable IC designers to map 0-In assertions to Axis' Xcite and Xtreme acceleration and emulation systems and leverage the power of assertions at hardware speed, which is typically 1000 times faster than software simulation, the companies said.
The joint solution is based on 0-In's ABV methodology and Axis' new Assertion Processor technology, which allows 0-In assertions to be run in Axis' Xcite and Xtreme acceleration and emulation systems. This can help to detect violations at the source and automatically generate reports that pinpoint the location and time of the problem.
Axis' Assertion Processor technology can map 0-In's pre-verified CheckerWare library and monitors into Axis' ReConfigurable Computing (RCC) engine, so designers can use their assertions throughout the design flow and perform assertion-based verification at acceleration and emulation speeds. Also, designers can access more than 30 industry-standard networking, memory and SoC interfaces from 0-In such as HyperTransport, PCI-X, AMBA, AGP, UTOPIA and DDR SDRAM.
Detecting violations at the source enables designers to know a problem has occurred as it happens, without having to wait for errors to propagate through the system. Such immediate feedback is made possible through the use of Axis' event-based, interrupt-driven system.
Magma Design Automation, Inc. appointed Gregory C. Walker to chief financial officer and vice president, finance. He will report to Roy E. Jewell, Magma president and chief operating officer. Walker has an extensive track record with EDA and other technology companies. His background includes six years with Synopsys, ultimately as vice president of finance and acting CFO. Most recently he was with Accrue Software as CFO and later interim chief executive officer. Prior experience includes various finance and planning roles with Integrated Device Technology, IBM's ROLM division and Xerox Corp.
Walker takes over for Robert Sheffield, who is leaving Magma after three years with the company for new professional pursuits. Walker holds an M.B.A. from the University of Rochester in Rochester, New York, and a B.A. in economics and history from Union College in Schenectady, New York.
Agere Systems announced it has engaged with Cadence Design Systems, Inc. to provide Agere customers with an ASIC design technology that can enable equipment manufacturers to deliver their products to market up to six months faster. The use of the Cadence tool can also help such manufacturers save hundreds of thousands of dollars in product design costs, the companies claim. Agere has contracted with Cadence to provide ASIC customers with a temporary license to use Cadence's First Encounter design tool, a virtual prototyping and hierarchical partitioning and placement system. Using First Encounter, Agere said the ASIC design “hand-off” package Agere receives from its customers will more closely represent the design's physical implementation and be of much higher quality than that provided in the traditional ASIC design flow. This new flow enabled by First Encounter will allow Agere to compress its back-end ASIC production schedule and accelerate delivery to customers.
Applied Micro Circuits Corporation (AMCC) presented Verplex Systems Inc. with its annual supplier award for excellence in the category of Quality and Reliability for Engineering Services. Verplex Applications Engineer Clay McKittrick was honored for providing superior on-site technical support. AMCC has quickly come to rely upon the quality of Verplex software for independent verification, ensuring that our chips are functioning correctly before they are fabricated.
LogicVision, Inc. formed a strategic partnership with SiidTech Inc., provider of the die identification technology, Silicon Fingerprinting. The partnership will explore the advancement, utilization and potential of silicon fingerprinting and embedded test in ASIC and SoC technologies, and revenue opportunities in silicon die ID and embedded test. SiidTech's technology provides the ability to identify uniquely each silicon die whether on a wafer or packaged. This capability -- based on the same principle of human fingerprinting that no two silicon dies are the same -- provides for many tracking and functionality options not possible with current ID and tracing methodologies, the company explained. And this technology, combined with embedded test, can provide test and yield management possibilities well beyond the wafer level to packaged parts. Complementary applications between the two companies include enhancing yields, significantly reducing debug and final test times, and more efficient field diagnostics. Combining SiidTech's Fingerprinting technology with LogicVision's embedded test could have a profound effect on closing the gaps between chip design, chip manufacturing through to systems development, the companies asserted.
AccelChip, Inc. and Elixent Limited said they are partnering to provide a direct path from MATLAB, the technical design language used by the majority of DSP designers, to D-Fabrix, Elixent's reconfigurable algorithm processor (RAP) architecture. The two companies are developing a version of AccelChip's behavioral synthesis tool, AccelFPGA, to produce optimized implementations of DSP algorithms targeting Elixent's D-Fabrix embedded RAP array. By implementing AccelFPGA in the D-Fabrix tool chain, Elixent can help reduce its customers' design cycles by several man-months through the automatic generation of RTL models and simulation testbenches. This technique also eliminates many risks associated with ambiguous written specifications that can cause unforeseen design iterations late in the design process.
Circuit Semantics Inc. (CSI) announced that has closed its latest round of funding, bringing the total amount raised to $11.9 million since its founding in 1997. Funds will be used as working capital to expand Circuit Semantics' technology development and sales efforts. Financing was led by Crescent Ventures Investors, headed by Kevin Hall, previously of Norwest Venture Partners, and included an equity investment from a leading computer manufacturer and Circuit Semantics strategic customer.
CoWare, Inc. appointed Peter J. Richards as vice president of worldwide field operations. He reports to Alan Naumann, CoWare's president and CEO and has responsibility for all sales, pre- and post-sales support and services activities worldwide. Richards comes from Simplex, now part of Cadence Design Systems, Inc. where he served as vice president of worldwide operations. Previously, he was vice president of Americas sales and operations at Wind River Systems Inc. Prior to Wind River Systems, Richards spent 16 years at Tandem Computers Inc., where he served in increasingly responsible roles. In his last position at Tandem, he was vice president of sales for its worldwide telecommunications business unit.
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--Ann Steffora, EDAToolsCafé Managing Editor

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-- Ann Steffora, Contributing Editor.

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