May 20, 2005
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

By combining new technology with the best of existing design methodologies, Synplicity's MultiPoint technology enables a methodology for the most critical design flow requirements, the company asserted. Specifically, MultiPoint synthesis provides better quality of timing and area results, faster runtime, the ability to handle very large designs, ease of project setup and constraint entry, and intelligent handling of IP blocks. The MultiPoint technology employs incremental design techniques that enable parts of a design to remain unchanged while others are synthesized. The technology creates interface logic models based upon user-defined "compile points," or instructions to the synthesis tool for modeling and synthesizing a particular portion of the design. Unlike other incremental flows where cross-boundary optimizations are difficult, the MultiPoint technology can optimize across design partitions using the same information needed for a top-down synthesis flow, enabling the highest design performance.
Synplicity also announced enhancements to its Synplify ASIC software easing the flow for designers to achieve high quality of results for complex SoC designs. The Synplify ASIC software now includes Synplicity's new MultiPoint synthesis technology as well as several new features to improve quality of results and runtime for high-performance ASIC design including case analysis and enhanced support for flows with Verplex Systems and LogicVision. The MultiPoint technology delivers a productivity-focused, scalable, memory efficient design methodology for optimizing across and within partitioned boundaries for large ASIC designs.
Customer Endorsements
Synopsys, Inc. reported that Texas Instruments has successfully used Physical Compiler, Synopsys' Physical Synthesis tool, to tape out multiple versions of its flagship TMS320C64x digital signal processor (DSP) chip. These next-generation 600 MHz DSPs, shipping today from TI, mark a milestone in performance for the company and will become the platform for most of TI's future DSP products, the companies said. The TMS320C64x DSP enables full convergence of video, voice and data on all broadband networks for TI's base station systems market. Using Physical Compiler, TI engineers saved two months in design cycle time and achieved timing closure on the 0.13-micron technology with 64 million transistors.
Synopsys also said that NEC's Computers Division has standardized on Formality 2002, Synopsys' equivalence-checking tool. Formality 2002 provides NEC's Computers Division with next-generation equivalence-checking technology that addresses the need for easy-to-use formal verification tools and delivers time-to-market advantages.
NEC chose Formality 2002 after an intensive evaluation, during which Formality 2002's capacity, performance and intuitive flow-based environment stood out above other available tools.
Simplex Solutions, Inc. announced that Oki Electric Industry Co., Ltd. has adopted Simplex's SignalStorm SoC as its sign-off delay calculator for its advanced ASIC and SoC designs. Oki selected SignalStorm SoC on the basis of superior accuracy, capacity, runtime and hierarchical design support. Oki will use SignalStorm SoC to speed timing convergence and help ensure first-silicon success for their advanced wireless, telecommunications and consumer-electronics designs.
Magma Design Automation, Inc. reported that Synergetic Computing Systems (SYCS) has licensed Magma's Blast Chip, an RTL-to-GDSII design system that uses gain-based synthesis and advanced place and route technology. SYCS has developed and patented a combined RISC -- DSP multiprocessor architecture called the SYNPUTER and intends to use Magma's system to get the architecture design to tape-out and demonstrate performance levels.
Magma also announced that Vitesse has standardized on Magma's RTL-to-GDSII IC implementation flow. Vitesse selected Magma as its EDA tool provider of choice after achieving better performance, reduced area and shorter design cycles on a number of designs using the Blast Chip integrated synthesis and place & route system and the Blast Plan hierarchical design solution. Blast Chip provided Vitesse with a complete RTL-to-GDSII design solution in a single executable. The production designs completed using Blast Chip include a 622 MHz, 100K-gate block, and another complex design with 500K placeable objects (approximately 2 million gates) and 160 RAM macros. Magma was able to meet timing and complete the design in just six weeks for Vitesse.
Silicon Metrics Corp. successfully integrated its SiliconSmart PATH into Banderacom's advanced COT (Customer Owned Tooling) design flow for its InfiniBand semiconductor products. With SiliconSmart PATH the Banderacom design team improved IC design performance by rapidly identifying, isolating, and correcting potential timing hazards in the timing analysis flow. Designers use SiliconSmart PATH to perform detailed transistor-level analysis with gate-level tools to uncover timing hazards that would otherwise go undetected, resulting in a silicon respin. The tool's 'what-if' analysis capability reduces timing analysis cycles from weeks to hours and drives the final design to a successful and on-schedule tapeout.
Banderacom's designers used SiliconSmart PATH's transistor-level analysis capabilities to obtain results that mirrored actual silicon behavior. With SiliconSmart PATH, transistor-level analysis became a fully automated extension to the gate-level static timing analysis (STA) environment. Transistor-accurate timing enabled Banderacom's designers to perform post-layout characterization of the paths in the design and guided design construction tools to take preventive and corrective actions.
Avant! Corp. entered into a strategic technology alliance with STMicroelectronics to develop and deploy concurrent IC and package design and analysis capability. As part of the alliance, the companies will work cooperatively to create a new paradigm that injects aspects of IC packaging into the early stages of chip layout.
The multi-year agreement will drive development of two new products: the first providing a physical planning environment bridging the IC and package domains, while the second will focus on parasitic extraction and package modeling. In addition, existing Avant! tools including the Milkyway database will be enhanced to support the concurrent IC & package design flow. Avant! also reported that Fast-Chip, Inc., a fabless semiconductor company delivering communication ICs to network OEMs, selected Avant!'s Milkyway-based, SinglePass-SoC tools for their PolicyEdge design, a complex, 100-million transistor Services Processor. Fast-Chip leveraged Avant!'s floorplanning; optimization, place and route; parasitic extraction; and custom layout editing features for the PolicyEdge design. Nassda Corp. said that Silicon Access Networks, Inc. used Nassda's HSIM to achieve fully functioning first silicon of 10-Gbps mixed-signal ICs for its iFlow Data Path Processing Platform, used in networking routers and switches. Silicon Access Networks replaced older "fast-SPICE" simulators with HSIM for all detailed timing verification of its entire iFlow IC family.
Magma and Fujitsu Limited of Japan announced that Fujitsu achieved one-pass silicon success using Blast Fusion and Blast Noise on a number of ASICs and SoCs, including a 4-million-gate, 0.18-micron design. The designs have been implemented in Fujitsu's CS71 and CS81 processes and are targeted for Japan's high-volume consumer products.
Oki Semiconductor and @HDL announced support of the @HDL software for use in the Oki Semiconductor ASIC Design Centers. Oki Semiconductor selected the @Verifier and @Designer products from @HDL after an extensive evaluation of competitive tools. The @HDL products will be used by Oki Semiconductor's ASIC Design Center staff to automatically uncover functional errors in customer designs, prior to release for silicon.
Improv Systems announced that Thrane & Thrane, manufacturer of global, high-speed satellite communications terminals, plans to use Improv Systems' multi processor Jazz DSP to create a next-generation ground station satellite communications modem.
Improv's Jazz-based platform design solution was chosen based on an extensive competitive analysis of available DSP technologies and was found to be the only one capable of meeting the performance requirements and throughput demands of the new satellite communications modem, the companies reported. The Improv integrated system allows the multi-processor DSP to be designed, modeled, and profiled as a single entity programmed in a high-level language. This approach allows the designer to rapidly iterate and close on an optimal hardware/software solution to meet the stringent application requirements. It further means that changes in requirements, and upgrades to the system can be satisfied by systematic refinements.
People On The Move
Xpedion Design Systems, Inc. added two new members to its board of directors, Moshe Gavrielov, CEO of Verisity Design and Alain Labat, president and CEO of Sequence Design. Both new members have extensive backgrounds in the EDA and semiconductor industries and represent the leading companies in their respective functional verification automation and design closure market segments.
Altera Corp. promoted Hiro Higuma to president of Altera Japan. Higuma, previously Altera's director of communications market strategy, will be responsible for developing and executing strategies to grow market share in the region and will report directly to George Papa, Altera's senior vice president of global sales.
MoSys, Inc. announced that Motorola Inc.'s Semiconductor Products Sector has licensed MoSys' 1T-SRAM embedded memory technology , which will be used to enable the incorporation of high performance, high density embedded memory blocks.
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-- Jack Horgan, EDACafe.com Contributing Editor.




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