Tality Corp. today announced Mindspeed Technologies, the Internet infrastructure business of Conexant Systems, Inc. has licensed its 10 Gigabit Ethernet Media Access Control (MAC) IP. It will be used throughout Mindspeed as the basis for their next-generation 10 Gigabit systems.
Cadence Design Systems also said last week it entered a joint venture to establish a software institute in Beijing that will train post-graduate-level engineers in electronic design. The joint venture is between Cadence Design Systems Asia Ltd. and Beijing Zhongguancun Software Education Co. Ltd. Beijing Vice Mayor Liu Zhi Hua and Cadence president and CEO Ray Bingham signed the agreement at an April 25 ceremony on the Cadence campus in San Jose.
According to Cadence, the Zhongguancun-Cadence Institute of Software Technology -- to be built from the ground up and expected to open in October -- will train up to 300 students in its first year; that capacity will increase to 1,000 students per year over the next five years. The campus will be located in the Beijing Zhongguancun Science Park, an area dedicated to research and development and other activities in a variety of disciplines, including integrated circuits, biotech and software. The joint venture is the latest instance of Cadence investing in China. In December, Cadence announced its intention to invest US$50 million in China to build a strong network of research and
development, customer support and services. Additional announcements are planned.
Cadence also expanded its strategic license agreement with Ericsson. The multi-year agreement gives Ericsson access to all Cadence electronic design automation (EDA) software, services and training to support its design operations worldwide. Cadence has been a strategic supplier of Ericsson for more than a decade and the new agreement represents the latest in a running series of collaborations by the two companies with an expansion to use Cadence's entire portfolio.
Synopsys Inc. said that Fujitsu Limited now offers support within its latest ASIC libraries -- the CS81series ASIC technology (0.18micron standard cell process) -- with the integration of Synopsys Physical Compiler into its ASIC design flow. Physical Compiler's unified synthesis and placement capability allows all aspects of synthesis, from architectural exploration to structuring and optimization, to have access to accurate placement-based interconnect delay information, instead of approximations from traditional wire load models. Availability of the latest Fujitsu ASIC libraries for Physical Compiler will allow Fujitsu ASIC customers to run placement themselves before
handing off the design to the Fujitsu. With this flow in place, Fujitsu expects to save weeks to months in design time to close post-route timing.
Monterey Design Systems signed an agreement with STMicroelectronics that would provide support of the Monterey System-Driven Physical Design (SDPD) solution by ST Central R&D and the Consumer and Microcontrollers Groups in their design centers. The use of Monterey SDPD on production tape outs has delivered major benefits in terms of productivity and design capacity. ST Central R&D recently completed the first 0.13-micron design using SDPD, demonstrating the suitability of the solution for this new technology, Monterey said.
Avant! Corp. reported that QuickLogic selected Avant!'s Nova-ExploreRTL mixed-language analysis tool to automate checks of VHDL and Verilog RTL design descriptions for compliance with QuickLogic's RTL coding guidelines. QuickLogic said it selected Nova-ExploreRTL analysis after an extensive evaluation of competitive tools. Nova-ExploreRTL supports a comprehensive set of built-in rules, coupled with its powerful Tcl programming interface for creating custom rules, to meet the RTL coding guideline requirements of leading-edge customers like QuickLogic.
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-- Ann Steffora, EDACafe.com Contributing Editor.