December 11, 2006
Model Based Approach to DFM – Clear Shape Technologies
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

How did you manage to early on to convince the foundries to work with you?

It is obviously highlighting the problem.  Designers over the last few years have become very cognizant of the problem.  People are seeing the issue from the design side with variation as is the foundries.  These are the real technology issues that everybody is starting to see.  It was more a matter of showing them that we have technology to solve the problem.  I think that the recognition that these problems exist and that they have to be addressed started to happen a couple of years ago.  The question really was "How are you going to do it?"  I think what needs to be done there was pretty much consensus that started to happen.  I would say that exists today.  It still was clear how it needed to be done and that's where we came in.

What is the pricing for your products?

Both of our tools, InShape and OutPerform, have a list price of $300,000 per year.  The other point is about these tools is that again because of the architecture they are linear in terms of distributive computing so that they can be scaled with the number of CPUs.

What is the typical customer environment?

The 65nm is just starting to ramp up.  That's where these technologies start to be adopted.  For example we expect them to use these tools actually not expect they are using these tools for cell design to begin with as you would expect.  You want your cells to be variation robust.  We expect them to be used at the block level and of course we expect them to be used for doing chip assembly.  In fact another part of the Cadence announcement is that we are integrating our tools into the SoC Encounter routing platform.  Clearly for us these tools are not only used by designers but also get integrated into the implementation environment.  The sue model will get resolved.  We expect people will use this in the same context as when they are doing DRC for cell, block and chip level designs.

When were these products first available?

InShape is a fully released product being used in production environment.  It was released in Q3.  The OutPerform product is in beta right now and we expect it to be released in the next few months.

Which month?

Early January.

How many customers are there now?

We are working with all the leading IDMs.  I have already talked about the foundries because the foundries have made announcements themselves.  As part of these announcements we have talked about Qualcomm and NEC.  There are a lot of endorsements by NEC in our announcements.  Cadence announced earlier that ATI is using our product in their flow.  These are the ones we announcing right now   But I can tell you we have already validated several other customers as well.

Obviously these products have relevance at 65nm and below.  Are there certain types of companies or applications where they are particularly well suited?

We do have some engagements at 90 nm.  If you think about it, the ultimate goal here in general and perhaps in particular is to extract them maximum value form your fab or your process technology platform.  You could do designs at 65 nm and 45 nm and get working silicon and perhaps even high yield.  The question is how much performance and area is left on table.  Even at 90 nm people start making compromises with recommended rules and this explosion of rules.  There are applications for our technology at 90 nm and people are using it there.  But you are right. The sweet spot is 65 nm and going down to 45 nm.  Because it is a fundamental problem that is dictated by manufacturing, it is difficult to segment by the type of application because anybody who is doing design and wants to extract the most from their process technology platform would use it.  Of course leading edge gut would get there earlier, right, because they are the one to first delve into the technology.

You stated that several companies supplying OPC and RET tools are doing so as mask editing tools.  Is there anybody out there with a similar approach more on the design side?

No, not in the manner we do it.  We haven't seen anybody that is tackling it like we are.  A lot of so-called DFM startups are actually trying to improve the OPC and RET side and the ones who are already there are trying to move it upstream like Mentor and Synopsys.  But that just doesn't work.  Like I said before that was part of the genesis of our company.  We had looked at most of these companies because they are all of the same timeframe.  We looked at what they were trying to do and nobody was doing what we are doing and that is how we got going in the first place.

Is this technology patented?

Absolutely!  That's something we are very cognizant of.  We do have significant patents.  We continue to file more to protect these technologies.

What do you see as the main challenge for the company moving forward?

The challenge is more of a macro challenge.  To be candid, I am not sure there is much that a company like ours can do about it.  I'll make a couple of points here.  Firstly, as a company that obviously had to work very hard with the fabs to get qualified both at IDMs and at foundries and then solve the problem on the design side.  The business model that EDA companies have make it harder and harder for even the large companies to get the value that is due for the complex problems being solved.  That's number one.  Number 2 is of course the general economic macro environment of where the semiconductor industry is today.  I think those are more the challenges than anything else.

Would you expand on the problem of the EDA business model?

EDA companies have to invest in where the money and the problems are today.  They can't in my opinion and don't really invest where the problems are going to be because they have to place bets on what the problems are going to be and what the solution is going to be and get it right.  They all fight for the current dollars.  But large and leading edge design companies at some point are looking at those design problems.  That's where they have to look at startups.  The problem arises because these companies also have multiple year agreements with these technology suppliers, sort of all you can eat deals.  The fight that these EDA companies have among themselves to gain dollars decrease the value designers want to pay.   Of course as a startup you have the luxury because you have been investing for three years and as an entrepreneur the first thing you have to do is to hope you are approximately right about the problem and the solution.   If you are, you can command a premium.   The macro environment is one that makes it hard.

« Previous Page 1 | 2 | 3 | 4 | 5 | 6  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, Contributing Editor.


Review Article Be the first to review this article

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automation of the UVM Register Abstraction Layer
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Virtual 2020 CEO Outlook Set for June 17
Colin WallsEmbedded Software
by Colin Walls
Multiple constructors in C++
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Software Engineer for EDA Careers at RTP, North Carolina
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Upcoming Events
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise