September 10, 2007
September Uptick
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

* The SPIRIT Consortium says they’ve partnered with Demos on Demand to create online presentations summarizing recent demos from various vendors showcasing their successes with IP-XACT. The demos are online and include content from ARM, Beach Solutions, Denali, Magillem Design Services, MataiTech, Mentor Graphics, NXP, Scarlet Code, and Synopsys.

* Synopsys announced that eRide is using Design Compiler Ultra to design its "Opus" GPS “low-power, high-functionality ICs, that include ultra-sensitive positioning technology to help wireless carriers reduce the costs.” Allen Chen, VP of VLSI Engineering at eRide, is quoted: "Advanced synthesis technology coupled with excellent support from the Synopsys team drove our decision to adopt Design Compiler Ultra for our next-generation Opus ICs."

* Synopsys also announced SHARP Corp. has evaluated Synopsys’ DFT MAX, and “has demonstrated in working silicon that this new small delay defect ATPG technology improves quality and is cost-effective when deployed with DFT MAX to compress the test data.” Synopsys said it has collaborated with both SHARP and STARC (the Semiconductor Technology Academic Research Center R&D consortium) to develop this ATPG technology.

Hiroyuki Shibata, Department GM in the LSI Test Engineering Department, Large-Scale IC Group at SHARP, adds: "We wanted to apply all the patterns without slowing down the production line or making costly changes to our ATE infrastructure. We achieved this by reducing the test data volume by 95 percent using DFT MAX to implement scan compression on-chip.”

* Synopsys announced, as well, that Tessolve has adopted Synopsys' DFT MAX. Per Mohit Bansal, Director of DFT Engineering at Tessolve: "DFT MAX is a straightforward extension of the standard scan techniques using Synopsys' DFT Compiler and TetraMAX ATPG design flows currently in use at Tessolve. Because TetraMAX supports automated diagnosis of DFT MAX-compressed test patterns, analysis of failed patterns on the ATE can be completed much faster and cost-effectively."

* Tsantes Consulting Group (TCG) announced that Toshiba America Electronic Components (TAEC) is now a client. Hideya Yamaguchi, Sr. VP at TAEC, is quoted: “We need to work with an agency that has a deep understanding of all aspects of the semiconductor business, how that business relates to the end consumer and one that also has close ties to the media. Tsantes Consulting Group is that agency.”

* X-FAB Silicon Foundries announced sales of $186.2 million for H1 2007, an approximate 69% increase over H1 2006. Per the Press Release: “The X-FAB Group attributes this growth to consistently high demand for its technologies and services, and its expansion including X-FAB Sarawak and X-FAB Dresden.”

* Xilinx announced that intoPIX will port its IP portfolio to Xilinx Virtex-5 platform FPGAs. Per the Press Release: “The intoPIX JPEG2000 encoding algorithm running on a Xilinx Virtex-5 FPGA, allows encoding at up to 120 frames-per-second (fps), over 20-percent faster than previous solutions. This creates the potential to create a multi-stream encoder delivering up to four channels of HD-SDI image management at 30 fps.”

Can you see me now?

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-- Peggy Aycinena, Contributing Editor.


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