November 19, 2007
Can One of the Big Three Compete in a Market Dominated by Others?
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Intel's Fundamental Advance in Transistor Design Extends Moore's Law, Computing Performance Built using an entirely new transistor formula that alleviates the wasteful electricity leaks that threaten the pace of future computer innovation, Intel Corporation today unveiled 16 server and high-end PC processors. In addition to increasing computer performance and saving energy use, these processors also eliminate eco-unfriendly lead and, in 2008, halogen materials.

Called the biggest transistor advancements in 40 years by Intel Co-Founder Gordon Moore, the processors are the first to use Intel's Hafnium-based high-k metal gate (Hi-k) formula for the hundreds of millions of transistors inside these processors. These Intel Core 2 Extreme and Xeon processors are also the first to be manufactured on the company's 45 nm manufacturing process, further boosting performance and lowering power consumption.

The new 45nm processors boast nearly twice the transistor density of previous chips built on the company's 65nm technology - that is up to 820 million transistors for quad-core processors, each using Intel's new formula.

Virage Logic Reports Fourth Quarter and Fiscal Year 2007 Results Virage Logic reported revenues for the fourth quarter of fiscal 2007 were $13.1 million compared to $11.3 million in the previous quarter and $15.0 million for the fourth quarter of fiscal 2006. Net loss for the quarter 2007 was $0.4 million, or $(0.02) per share compared to a net loss of $1.2 million, or ($0.05) per share, for previous quarter and net income of $0.8 million, or $0.03 per share, for the same period a year ago. For fiscal year 2007, revenues were $46.5 million, down 22 percent compared to revenues of $59.3 million reported for fiscal year 2006. GAAP net loss for fiscal year 2007 was $4.6 million, or ($0.20) per share, compared to a net loss of $0.9 million, or ($0.04) per share, for fiscal 2006.

Special Report: Blown Away in San Francisco - Cool Stuff at the HP/Intel Worldwide Quad-core Event David Heller reports that he was privileged to attend HP and Intel's Worldwide Quad-core Event in San Francisco. These types of events are usually, to me any way, just marketing hype ... but this one was different .. it was revolutionary!

HP and Intel have really done something monumental. Last year HP introduced workstations based on Quad-Core Intel® Xeon tm processors and at this event they unveiled their next round of eight-core workstations, the HP xw660 and HP xw8600 powered by the latest generation Quad and Dual-core Intel Xeon processors.

But, what made the event revolutionary was being able to see first hand what customers have done, and how they have saved time and money over the past year using HP's initial Quad-core computers. Examples cited in the article include design of race/street car kit, photo-realistic architectural video tour, a geological profile of the entire North Sea

Other EDA News

  • Phylinks Announces Working-First-Silicon for PHY-820: PCIe PHY with Leading-Edge DFT Features
  • Ansoft Corporation Net Income Increases over 40%
  • SynTest Receives A Fundamental Patent on At-Speed Capture Invention for Scan ATPG
  • The MathWorks Delivers Key Capabilities for Parallel Applications, Multithreaded Computations, and 64-Bit Platforms
  • PhaseLink Selects Berkeley Design Automation Analog FastSPICE(TM) for Full-Circuit Verification of Frequency Timing Generation ICs
  • DTS(R) Audio Technologies for Blu-ray Disc and HD DVD to be Added to Tensilica's HiFi 2 Audio Engine
  • Agilent Technologies Announces Productivity Breakthroughs with Advanced Design System 2008 EDA Software
  • Mentor Graphics and TSMC Collaborate to Release 65 nanometer RF Design Kits
  • Temento to Delivers Integrated FPGA Hardware Debug Solution for Mentor Graphics Precision Synthesis Customers
  • Optimum Design Associates Inc. (OPTIMUM) announces that Everett Frank has been named Vice President, General Manager (VP, GM).
  • Carbon Design Systems Adds Support for Latest Version of ARM Tools
  • Atrenta Announces University Technical Advisory Board
  • HP Advances Flexibility, Efficiency of Blades Across the Data Center
  • GiDEL(TM) Demonstrates Tightly Integrated Toolset for Accelerating C Algorithms in High-Powered FPGAs
  • Temento Launches an Innovative Business Model for Its 'Dialite' Debug Platform
  • Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips
  • The Mathworks Integrates Tools to Distribute Simulink Models to Multiple Processors
  • New Earth Modeling Technique Improves Design of Low- and Zero-Profile Antennas

    Other IP & SoC News

  • Xilinx Chief Willem Roelandts Elected SIA Chairman
  • Data I/O Corporation Introduces New Automated Solution for Flash Media Duplication, Supporting Flash Cards and BGA Format SD & MMC Solutions
  • Global Unichip Selects Vivante Graphics Solutions for Mobile System On Chip

    « Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

    You can find the full EDACafe event calendar here.

    To read more news, click here.

    -- Jack Horgan, Contributing Editor.

  • Rating:

    Review Article Be the first to review this article

    Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
    Senior Software Architect Internet for EDA Careers at San Jose, California
    Sr. Application Engineer for Mentor Graphics at Fremont, California
    Hardware Engineer, Board Design for Arista Networks at Santa Clara, California
    Salesforce Technical Lead   East Coast  for EDA Careers at Cherry Hill, New Jersey
    Upcoming Events
    DVCon U.S. 2020 at DoubleTree Hotel San Jose CA - Mar 2 - 5, 2020
    OFC 2020 - The Optical Networking and Communication Conference & Exhibition at San Diego Convention Center San Diego CA - Mar 8 - 12, 2020
    DATE '2020 at ALPEXPO Grenoble France - Mar 9 - 13, 2020
    NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 22 - 26, 2020

    © 2020 Internet Business Systems, Inc.
    25 North 14th Steet, Suite 710, San Jose, CA 95112
    +1 (408) 882-6554 — Contact Us, or visit our other sites:
    AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
      Privacy PolicyAdvertise