September 29, 2008
SiP or System-in-Package
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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For several years I have been writing about the alphabet soup (SoC, FPGA, PCB and IP) that is the EDA arena. This time I decided to look at SiP or System-in-Package, which some see as an alternative To SoC and some see as a complement to SoC. I had a chance to discuss SiP and IC packaging in general with Keith Felton who describes himself as “the product marketing person at Cadence with the enviable job of being responsible for IC Packaging and System-in-Package technology.” We talked about what SiP is, who uses it, what challenges it address and what the benefits are.

Would you provide us with a brief biography?
I’ve been with Cadence for 10 years in a product marketing role. Initially I was focused on PCB but for the last 7 years I focused solely on IC packaging and then System-in-Package as we brought out our first SiP solution a couple of years ago. Before that I worked at Viewlogic for a couple of years, where I worked on their high speed PCB solution. At the time it was called ISIS. Prior to that, I spent 8 years in Europe working for a company known as Racal-Radac. They later got bought by Zuken. When I was at Redac-Zuken for those 8 years, I was responsible for their PCB product, known as Visula. Before I got into EDA, I was a design engineer for a wireline telecom company in the UK that got acquired by Northern Telecom.

Would you give us an overview of IC packaging and SiP and how they related to SoCs, PCBs, …?
First of all, you have the traditional IC packaging. Typically in IC packaging you are taking a finished chip that has been fabricated, the wafer has already been sliced and diced. You are literally putting it into the package. You are designing the package as a physical layer entity. You obviously have to capture the layer connectivity between the correct pins on the chip and the correct balls, bumps, pins on the package. Then it is pretty much a straight constraint driven place and rout environment. That is where Cadence has been for quite a number of years. It is an Alegro package design solution. It has been pretty much focused on package layout construction for what I call backend chip whether those are analog, RF, SoCs, ASICs or maybe even memory chips. It is a matter of taking one or maybe more chips and assembling them together in usually the lowest cost package with the smallest form factor, bearing in mind such things as signal integrity.

When system-in-package came around, it differentiated itself in that what you are doing is actually mixing not just the chips but also discrete components together in a package usually to form some sort of subsystem. Let’s call it a chip set within a single package rather than have individual packages on a PC. Typically early SiPs were very common in the wireless communication space, where, for example, you want the complete CDMA solution. If you were Apple building the next iPhone, you do not want to have to construct a CDMA front end out of multiple chips because that is not your area of expertise. You want to buy a single package that is in fact the wireless front end for a cell phone and just have that in a single package, connected by the appropriate connections to the package and presto, you now have a cell phone. The wireless space, predominantly battery powered technology handsets or some other forms of wireless devices, has by far the largest influence on the SiP. This is the market, where the IC company needs to provide the largest value add to its customers. And of course they want to sell all of their chips. They do not want you to buy different baseband chips or different power amplifiers. If they can combine all of the functionalities for a wireless device in a single chip, then it is not only easy for their customers, the system companies, to consume that function but also it means they sell basically all their chips in one package. So they maximize their ASP. The reason they do it as a SiP rather than a SoC is that, first of all, SoCs have a long engineering timeline and they need significant volume to recoup NRE. That is always a challenge in the wireless market where technology standards are changing so often that silicon really does not have a long lifetime. They are always changing some part of the system. That is one of the reasons why people are turning to system-in-package, a combination of multiple chips together with discrete as oppose to a SoC implementations. The other area which tends to be more predominant is that when you do a SoC, you have to pick one process to do that SoC in. When you are talking about analog, RF and wireless, you are talking about multiple processes and multiple process nodes. If you are doing a power amplifier, for example, you might want to be silicon germanium or gallium arsenide rather than CMOS. It is hard to try and develop a mixed single SoC when you have to pick one technology to implement. Of course, it is always a compromise for the other areas. You have the problem with that. That hinders size, performance, cost and other factors. As I have said, technology is changing so rapidly that the lifecycles of products is pretty short. You are always updating one of the chips. In the wireless front end system there are new carrier standards like 3G coming. You want to add the latest in streaming video, voice features or something like that. Most companies look at system-in-package as a really effective way of integrating multiple functional pieces of silicon together in a very cost effective and efficient space. That does bring about some challenges. One of them is co-design. If you need to integrate multiple chips in the same package, you really need to affect the layout of each chip so that they can interconnect and interoperate together optimally. You can not just take a handful of disparate chips and throw them together in one package and expect them to have an efficient implementation. You have to do what would be co-design, which, in a nutshell, is to edit the IO tag ring of each die in the package so that they can connect together in the most efficient fashion. So co-design is almost a mandatory requirement for anyone doing system-in-package.

In addition to cell phones, what other applications would likely use SiPs?
Another very common area for SiP is in memory. When you look, for example, inside your SanDisk compact flash card in your camera, you will find SiPs all stacked together. That is including the memory controller. You will find a number of discrete components down on the substrata of that package. Unbelievably that is all in something as thing as an SD memory card. There are four to five dies on that little guy and that includes the microSD memory card. They still fit four to five dies inside of those. Another area is things like the world of multimedia processors, where you are looking at something in an HD set-top box and where you have the actual ASIC itself for processing the digital input and converting it to HDMI for the output; you know something like 7.1 Dolby. Often because of the amount of power required, they will use a system-in-package or a package-on-package which you would call a derivative of SiP. That is where you take a set of memory chips and stack them together in a package. Let’s say that there is a center package and you set that directly on top of another package with direct package-to-package interconnect. Then you have what is called a package-on-package. The reason they do that is, as you know, the memory market is a commodity market. You can never tell exactly in what form factor your memory chip will be supplied. Memory suppliers are always changing processes to optimize yield and reduce cost. As I said, it is a commodity market. If you try to design a memory chip directly on top of your processor, there is a high degree of likelihood that the footprint of the memory chip is going to changing slightly depending on who is supplying you. Let us say it is a Samsung. Samsung could change production to a new technique halfway through the production. They still supply you with your 2G memory chip but it has slightly different pin-out or form factor. So trying to design what is a commodity and changes rapidly is difficult. So what they try to do is ask Samsung to send them packaged memory chips. Let Samsung worry about the changing form factor but put it into a standard JDEC package. Then the company will integrate the package on top of their own package using standard JDEC footprint. They know that the pins and signal names are going to be in the same location.

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-- Jack Horgan, Contributing Editor.

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