Olympus-SoC supports the Unified Power Format (UPF) throughout the netlist-to-GDSII flow, including the ability to describe design intent through power state definition tables.
Unlike most of the products from the other vendors covered in this article, Prolific's ProTiming is a tool designed to work with Synopsys Prime Time. Unlike other optimization tools, which modify RTL, the standard-cell libraries, or placement, ProTiming is a final-pass solution that is run on a "completed" design. ProTiming runs Synopsys' PrimeTime to measure performance. ProTiming performs design-specific timing optimization during the static timing analysis step of the physical design flow. The software makes use of cells already existing in the library and can provide a 5-10% performance increase without modifying RTL or adding new cells to the library. If desired, ProTiming can also specify new cells that are created as needed, either by traditional methods or automatically by Prolific's ProGenesis tool suite, for an additional 5-10% performance increase.
The result before and after the final pass timing optimization are consistent with the Prime Time results, since the RTL has not been modified. In conjunction with PrimeTime SI, ProTiming also fixes signal integrity problems and removes hold time violations. Improvements are gained in addition to any optimizations that were made earlier in the design process. ProTiming minimizes the impact of its changes on the design, and produces a change file for an ECO, if required.
ProTiming also supports a more aggressive approach; ProTiming will replace all cells after STA with low L (low power) or half drive strengths, then fix timing by increasing the drive strengths only in the critical paths required to meet timing. The company claims that this methodology results in power savings of up to 20% or more.
Simucad's AccuCore is not a traditional STA tool, and, just like ProTiming does not aim to replace Prime Time or any other full circuit STA tools. AccuCore is a block characterization and modeling tool that uses STA techniques to achieve the following goals.
- Generates Synopsys' Liberty (.lib) timing models, generates a gate-level verilog netlist and generates or reads DSPF files for STA
- Exports fully sensitized SPICE deck for selected critical paths and clocktrees with measurements
- Automatically partitions blocks into cells
- Automatically extracts cell functions and generates vectors required for accurate SPICE characterization
- Includes fast API-based SmartSpice characterization engine
- Complete block and full-chip gate-level STA environment for rapid bottleneck analysis and timing verification.
Ever since the beginning of the EDA industry, tools developers have had to trade off accuracy with execution speed. Low execution speed means that designers are idle while waiting for results in order to fix bugs or improve the quality of the design. Lower accuracy may mean that a circuit which is thought to be good will either not have good yields or have functional faults. Although in the previous century market conditions could allow companies to accept slower execution speeds in favor of accuracy, today consumer driven markets make this choice unrealistic.
The penalty for not being first in the market, or for missing the optimum release date, often means the loss of million of dollars. Tools must be both accurate and fast in order to keep development time to a minimum. Unfortunately for EDA vendors, circuit sizes continue to increase, and smaller process geometries increase the complexity of the analysis by requiring designers to consider more and more parasitic effects that can negatively impact the performance of their circuits.
Credit must be given to EDA vendors for continuing to improve the tools to meet the new challenges. It is unfortunate that the EDA industry has not yet found a way to generate profits commensurate to its contribution to the semiconductors and entire electronics industry.
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-- Gabe Moretti, EDACafe.com Contributing Editor.