Assuming consummation of the terms of the agreement, Synopsys will pay $12.00 cash per Virage Logic share, resulting in a transaction value of approximately $315 million, or approximately $289 million net of cash acquired. The transaction is still subject to regulatory and Virage Logic shareholder approval, as well as other customary closing conditions.
The boards of directors of both companies have already approved the transaction, under which current Virage Logic President and CEO Alex Shubat will join Synopsys. After the closing, Virage Logic will become part of Synopsys, and Virage Logic stock will cease trading. The transaction is expected to close in the fourth quarter of Synopsys' fiscal 2010 (i.e. between November 1, 2010 and January 31, 2011). Therefore, Synopsys anticipates the transaction will be neutral to its non-GAAP earnings per share in fiscal 2010, and accretive in fiscal 2011 (i.e. beyond January 31, 2011). "With more functionality being integrated into a single device, high-quality IP continues to be key for enabling designers to reduce integration risk and speed time-to-market," said Dr. Aart de Geus, chairman and CEO at Synopsys. "Bringing Synopsys and Virage Logic together broadens our portfolio and builds on two very strong technical teams. It is also in line with what so many customers are looking to Synopsys to address: a way to quickly incorporate standard functions into their SoCs so they can focus on developing differentiated products."
"When I co-founded Virage Logic in 1996, it was with the belief that a semiconductor IP company could provide the technically superior building blocks that the industry needed to accelerate development of high quality, cost-effective end products," said Dr. Alex Shubat, president and CEO of Virage Logic."Today, the transition to a fabless, or 'fab-lite' model, coupled with the explosion in SoC product development costs at the advanced process nodes, has resulted in an escalating need by the semiconductor manufacturers for production-proven IP. By joining forces with Synopsys' impressive engineering team and by gaining access to their global channel, we will be able to accelerate the development and delivery of our broad product offering to help customers meet their design-for-profitability goals. I am excited to join Synopsys to further my original vision."
[4] Footnote: Sample section of EDAC MSS specs for reporting SIP revenue (one of multiple pages):
5.1.4 SIP Management: Software tools for SIP database management, delivery, and publishing.
5.1.5 Royalty-Based SIP: Semiconductor intellectual property that does not fit into any previously defined category, and/or revenue obtained for the "right to use" of intellectual property in the development or manufacture of a semiconductor. Examples of "right-to-use" intellectual property include royalty fees paid for the use of an EDA tool, or fees paid for a license to manufacture using intellectual property in the form of a unique methodology, process recipe, architecture, or other proprietary technology. Specific examples include royalty fees paid for the right to incorporate an OPC technology into a design, or the right to include BIST technology into a design, paid for in the form of a royalty.
5.1.6 Library Characterization: Software tools used to characterize standard cells, I/O, macro or memory SIP and generate the timing, noise and power libraries required for analysis, synthesis and physical implementation tools.
5.2 Macrocells and Cores
5.2.1 Physical Libraries: The class of building blocks or elements used to assemble or compile a virtual component into a particular target process. The library provides a physical representation of the logic and functional elements of the design.
5.2.2 Memory Elements: Any storage element, from circular buffers and memory cells up to complete memory blocks.
5.2.3 Non-Volatile Memory: Memory that retains its state without any power supplied.
5.2.4 Analog and Mixed Signal: An IP block or virtual component with circuitry that provides analog functionality, usually requiring additional considerations over standard digital SIP.
5.2.4.1 RF: Virtual components and interfaces for wireless radio-frequency physical media interfaces.
5.2.4.2 Components: Includes A/D, D/A, comparators, amplifiers, detectors, pulse compression, sources, switches, PLL/VCO, reference/regulators, pulse-width modulators, and other components.
5.2.4.3 Signal Processing: Includes filters, couplers, doppler, target and clutter, mixers, and multipliers/dividers.
5.2.5 Arithmetic, Mathematic, and Logic Functional Blocks
5.2.6 Interface/Peripheral Cores: Interfaces and peripherals (in the form of software or RTL) that conform to recognized standards, or which perform standard functions such as timers or keyboard controllers.
[5] KEY DEFINITIONS: COMPLETE LIST:
A partial list is included below as a sample. Click on the URL above for the complete list.
IP (Intellectual Property)
A broad category of written and electronic material that is legally recognized as proprietary to a specific organization. In the electronics field, intellectual property refers to specific portions of a chip or “building blocks” which may be proprietary and/or patented designs of a particular company. These reusable blocks or “cores” may be made available commercially to others as portions of new designs. See also SIP (Semiconductor Intellectual Property) and VC (Virtual Component).
SIP (Semiconductor Intellectual Property)
A block of a design or testbench that can be reused. Also known as a virtual component.
SoC (System on Chip)
A single chip on which multiple specialized blocks of logic have been combined. These blocks, which consist of Semiconductor Intellectual Property (SIP), may be sourced from a company's internal portfolio, or from commercial providers who are external to the company.
testbench
A custom model of the system environment used during the verification of a design to provide simulation inputs and respond to simulated outputs from the design under test.
VC (Virtual Component)
A reusable block of semiconductor intellectual property (SIP). VCs may be soft (synthesizable), firm (parameterizable), or hard (where the layout is fixed, with only the I/Os visible to the design tools).
[6] Footnote: The author of this issue of EDA WEEKLY entitled, "The State of IP" was pleased to receive an email from one Yvette Huygen Deshpande, Director, Worldwide PR & Corporate Communications, Synopsys, Inc. on August 18, 2010. Yvette kindly pointed out that in a supplement to its standard quarterly financial reports, Synopsys did indeed publish the revenue results of several categories of its Product Groups, of which "IP & Systems" is one.
Synopsys defines this product category as "Intellectual Property and System-Level Solutions." Synopsys' IP portfolio provides customers with silicon-proven digital, PHY, analog and verification IP for SoC designs to reduce their design risk and time-to-market. Its IP solutions include the DesignWare® Library of infrastructure IP, VCS Verification Library of popular chip function models, and DesignWare Cores, which are pre-designed and pre-verified digital logic and mixed-signal blocks that implement important industry standards, including USB, PCI Express, DDR, SATA, HDMI, Ethernet and MIPI. Its analog IP solutions include analog-to-digital converters, digital-to-analog converters, audio codecs, video analog front ends and touch screen controllers. Our System-Level solutions enable customers to, among other things, accelerate verification and embedded software development. These solutions include Synopsys virtual prototyping portfolio and Confirma™ Rapid Prototyping System, the portion of the Certify®, Identify Pro, and Synplify Premier software tools used for system verification, and Synphony High Level Synthesis.
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