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DAC Wrap Up Report
The organizers of the Design Automation Conference
(DAC) released attendance numbers for the recent 39th annual DAC held in New Orleans. Total attendance was more than 9,500, however, only about 4,300 attended the technical program, meaning that more than half of the attendees were exhibitors and others. Of the vendors I visited with, many were actually filled to capacity in their demo suites, busily garnering quality leads, however, the show floor at times was like a ghost town. Next year's 40th annual DAC in Anaheim is expected to be better attended due to better proximity for many potential attendees.
Many of the audio and visual presentations given during DAC, including keynotes by Hajime Sasaki, chairman of the board of NEC Corp. and Jerry Fiddler, chairman and co-founder of Wind River Systems
are available at
During the show, the EDA Consortium
presented the 2002 Design Achievement Award to Philips Semiconductors'
Nexperia silicon system design team for its design of the Nexperia-based pnx8500, a highly integrated multimedia-processing chip.
For more on this design, please see
for the technical paper from Philips.
In other news of note from the recent weeks, Synopsys, Inc.
announced that its Professional Services organization is offering a new design service meant to enable licensees of IP cores from ARM
to realize the advantages of “soft” IP and the ease of adopting new, customer-preferred silicon technology combined with the performance, predictability and time-to-market benefits of “hard” IP, the company said. The aim of Synopsys' Core Hardening service is to address the key implementation stages of hardening an ARM microprocessor core described at the “soft” register-transfer-level into a manufacturable GDSII description for the target silicon
process technology and end-user application.
Synopsys reported that it has already successfully completed core-hardening projects undertaken directly for ARM as part of the ARM Foundry Program. The Synopsys design team recently delivered the ARM946E-S core for production using TSMC
's 0.18-micron technology, completing the project on time and meeting the required performance benchmarks for speed and silicon area.
also introduced Floorplan Compiler, a hierarchical design planner that is meant to enable designers to save time and money by creating high quality floorplans with less iteration. Building an efficient hierarchical floorplan is typically difficult and time-consuming, requiring numerous iterations, the company explained. Floorplan Compiler's virtual flat approach solves this problem by eliminating the ping-pong effect that normally occurs between chip-level and block-level floorplanning. According to Synopsys, the result is a product that enables all critical floorplanning decisions such as partitioning, block shaping, macro placement, pin assignment, and feed-through
optimization to be made in the full context of the chip, including blockages and routing hotspots.
Mentor Graphics Corp.
released its FAST (FPGA Advantage Solutions Thrust) Partner Program that provides third-party FPGA design centers with its hardware description language (HDL) design flow FPGA Advantage, along with assessments, training and certification in field-programmable logic design methodologies from Mentor Consulting.
Mentor explained that through this program, FPGA design firms will gain access to the latest Mentor Graphics tools and expertise, and manufacturers will be able to easily identify resources that have been trained by Mentor Consulting on FPGA design methodologies.
The first partner in the program is North Shore Circuit Design
, based in Austin, Texas. Founded in 1991, the company staffs 20 circuit designers, layout designers, engineers and programmers.
Also from Mentor Graphics
, its Embedded Systems division announced with First Silicon Solutions (FS2)
a set of integrated tools to simplify and speed development of multi-core system-on-chip (SoC) devices based on the MIPS
4KE processor family. The new tools were selected by Silverback Systems
, a start-up developing silicon and software solutions for networked storage and data centers.
Also at DAC, Synopsys
presented Mentor Graphics
with the second annual Tenzing Norgay EDA Interoperability Achievement Award
. Mentor Graphics was recognized during the Open Source Interoperability event for its support and promotion of EDA standards that further interoperable design flows. Synopsys established the Tenzing Norgay Interoperability award last year in order to encourage EDA providers to collaborate on interoperable design flows that benefit the user community. The award is presented annually to an EDA company that has surpassed common levels of interoperability, has contributed to overall industry advancement, and has helped provide a new view of the future
for EDA interoperability.
Mentor was recognized for applying open source standards Liberty and Synopsys Design Constraints to a broad array of Mentor tools to ensure consistency and interoperability throughout a multi-vendor design flow. Mentor also supports committee-generated standards, and currently chairs the Accellera standards organization. As one of the first licensees of Liberty, even prior to its open source standardization, Mentor demonstrated its willingness to improve EDA interoperability through new methods of standardization. Mentor has also developed unique technical solutions to ensure that the SDC standard guides its tools in a consistent and correct manner.
Cadence Design Systems, Inc.
and Agilent Technologies, Inc.
announced a new solution meant to enable design engineers to shorten product development time; lower design costs, and focus on creating innovative communications products. The fusion of the two companies' technologies, the Agilent RF Design Environment (RFDE), is the first product to result from the alliance the two companies formed last February.
According to the companies, the RFDE RF EDA software platform tightly integrates Agilent's leading RF simulation technologies into the Cadence industry-standard analog/mixed signal design flow framework and is expected to reduce the development time required for large-scale RF/mixed-signal ICs used in wireless and wireline appliances.
is now shipping version 5.0 custom IC release, which the company said enhances its custom IC design solution for faster time-to-use of new D/MS process technologies and provide superior D/MS chip-level integration. New features in Cadence Chip Assembly Router provide a unified chip assembly environment running on the OpenAccess database, which merges large cell based digital designs created within Cadence SoC Encounter with custom digital, analog, mixed-signal, and RF content.
Expanded place&route capabilities for custom digital, analog, RF block, and IC creation are integrated within Virtuoso XL's custom layout editor. The single design cockpit enhances block-level custom IC design, with yield prediction technology added to smooth the path into the foundry for manufacturing of CMOS-based ICs. Cadence also has extended its verification capabilities by adding VHDL-AMS to its existing Verilog-AMS capability.
The Institute of Electrical and Electronics Engineers
(IEEE) has honored Cadence
with its 2002 Corporate Innovation Recognition award, citing leadership in the field of electronic design automation tools and systems that has “resulted in major advancement of the arts and sciences of electrotechnology.” Cadence President and CEO Ray Bingham accepted the award on June 22 at the annual IEEE Honors Ceremony in Toronto. Cadence is joined by two other corporate honorees this year -- Seiko Epson Corp.
and Taiwan Semiconductor Manufacturing Company
reported that by using design tools from Cadence
, specifically NeoCell, it has reduced the turnaround time needed for its most challenging analog RF IC physical designs with 0.25-micron BiCMOS process technology by approximately 30 percent. With Cadence and its distributor, Innotech Corp. Hitachi
was able to achieve this significant improvement in design productivity by adopting Cadence automated custom physical design methodology. Since the analog IP is captured as constraints in the schematic and can be re-used, Hitachi said it believes it will be able to reduce the time to generate derivative of physical designs by 50 percent.
Numerical Technologies, Inc.
released a new version of its CATS mask data preparation software for increased throughput of advanced photomask manufacturing. The company said CATS version 23 utilizes an improved hierarchy management system and its scalable distributed processing architecture to virtually eliminate the lengthy times required to convert the massive databases associated with advanced photomasks into mask write and inspection formats. Also, CATS version 23 utilizes advanced fracturing algorithms designed to improve the manufacturability of subwavelength photomasks.
The CATS software “fractures” an IC design database into individual layers and shapes to prepare this data for mask write tools and inspection machines. With the addition of optical proximity correction features, the amount of data in a given database has grown rapidly. In addition, preparing data for shape-based mask write tools, used for subwavelength photomask manufacturing, requires complex, compute-intensive algorithms.
announced that its Silos III logic simulation software for semiconductor technology design analysis and validation is featured in two recently published books about Verilog HDL – Verilog Quickstart
(Third Edition) by James M. Lee and The Verilog Hardware Description Language
(Fifth Edition) by Donald E. Thomas and Philip R. Moorby. Both publications, which provide fundamental and practical language instruction, are updated with comprehensive information about the new IEEE 1364-2001 Verilog standard features. A CD-ROM containing Simucad's Silos simulator accompanies each book to complement the subject matter.
Another book, Advanced Digital Design with the Verilog HDL
by Michael Ciletti is scheduled for release by Prentice Hall in August. The book is written for advanced digital design courses and for design engineers who need to know how to use a hardware description language at key stages of a digital circuit design from verification to synthesis. Included with the text is Simucad's Silos III software.
The X Initiative
awarded its first annual X Achievement Award to DuPont Photomasks, Inc.
in recognition of its outstanding contribution to the success of the X Architecture. The award was presented as part of the X Initiative's First Anniversary Forum, held in conjunction with the Design Automation Conference. The X Initiative steering group selected DuPont Photomasks from the 33 member companies as having made the most significant contribution to the mission of the X Initiative during the past year.
has been contracted by the Defense Advanced Research Projects Agency (DARPA)
to develop design tools for integrated three-dimensional electronic circuits. DARPA manages and directs selected research and development projects for the U.S. Dept. of Defense.
The contract was awarded by DARPA's Microsystems Technology Office as part of its Automated Design Tools for Integrated Mixed Signal Microsystems (NeoCAD) program. For the DARPA project, Syncron will address the global modeling and simulation of electronic circuits; develop predictive planning tools that consider the full constraints imposed by electro-thermal and signal integrity; and demonstrate the feasibility of designing 3-D architectures with acceptable performance.
Syncron will integrate the new technology into its Universal Design Network (UDN), an integrated group of proprietary software systems -- including design project management, collaboration, parts management, design and design verification -- that greatly reduces design iterations and eliminates interoperability concerns. Administered entirely via the Web, the UDN connects project users through peer-to-peer deployment, whereby the software overlays into existing design systems, allowing all participating engineers to share parts and design data.
announced the advancement of an alliance with Cadence Design Systems
to broaden the reach of EDA using Linux. As part of this, Cadence has furthered its investment in HP IA-32 and Intel Itanium-based servers and workstations running Linux for deployment in its development, testing and customer support programs.
The companies' efforts are part of a strategy to provide powerful yet economical solutions for customers using the combination of an open-sourced operating system, industry standard 32- and 64-bit systems and market-leading EDA applications. The first applications from Cadence to exploit Linux on Itanium-based platforms will be its family of Physical Verification solutions, used in the manufacturing of integrated circuit design.
Accellera, the EDA organization focused on language-based electronic design standards, approved SystemVerilog 3.0 as an Accellera standard. SystemVerilog extends the Verilog hardware description language (HDL) to support architectural and behavioral design and system verification with assertions. SystemVerilog supports the built-in C types to provide a clear translation to and from C for better encapsulation and code compaction. The C types also give users improved methods to create algorithmic models and advance the abstract syntax a designer can use to create efficient synthesizable code. Other synthesis improvements include enhancements to the “always” block to avoid
simulation and synthesis mismatches. With SystemVerilog, designers can also specify intent with their simulation, synthesis and formal verification tools.
Synopsys announced its support for SystemVerilog 3.0 and donation of several technologies to Accellera for SystemVerilog version 3.1. The donations include testbench modeling capabilities, OpenVera assertions, a C/C++ model interface and a coverage application programming interface (API) that provides links to coverage metrics.
European electronics research center IMEC launched an industrial affiliation program (IIAP) that will focus on technology for reconfigurable systems. Within the program, IMEC said it would develop design technology for reconfigurable systems targeting networked portable multimedia appliances.
IMEC said that over the past three years, it has built up extensive expertise in design technology for embedded computing platforms containing instruction set processors in combination with reconfigurable hardware. Therefore, the mission of its new IIAP is to build design technology, which enables the programming of heterogeneous reconfigurable platforms with the same ease of use as current technology allows for general-purpose processors. Program activities will include the development of an operating system that enables true hardware/software multitasking and the integration of interconnect networks on silicon for task-level reconfiguration in reconfigurable hardware.
The new IIAP will focus on reconfigurable systems technology targeted for networked portable multimedia appliances but the results will be much more generic and useful in other application domains, IMEC said. Multimedia applications such as MP3 players, Internet browsers and games running on portable devices such as PDAs and phones are computationally intensive and have a lot of parallelism, which prevents them from being implemented on general purpose embedded processors. Reconfigurable computing would not only provide a solution to this problem but also addresses flexibility and computational power issues.
IMEC invites potential partners, most likely providers of technology for reconfigurable systems and system houses targeting reconfigurable platforms, to participate in this program expected to run over 3 years.
IMEC also said it joined the Open SystemC Initiative (OSCI), in order to make its proprietary OCAPI-xl design environment compliant with the SystemC standard. CoWare, Inc., founded with technology originally developed at IMEC and a founding member of OSCI, contributed hardware/software modeling to the SystemC language and co-developed the SystemC reference implementation. Over the past half year, IMEC said it has played a major role in defining the requirements for SystemC 3.0 within the OSCI language working group. SystemC 3.0 will provide capabilities for describing hardware and software tasks, flexible hardware/software partitioning, and hardware/software simulation of the overall system
whereby the software tasks run on a simulated RTOS. IMEC's proprietary OCAPI-xl design environment features dynamic behavior and multi-threading and has an automatic code generator from C to synthesizable register-transfer languages for hardware and to C processes on OS for software. However, IMEC said current RTLs do not support multi-threading and dynamic behavior of systems consisting of both hardware and software. SystemC 3.0 will bridge this gap.
Real Intent said will add support for the SystemVerilog DAS (Design Assertion Subset) to its flagship product Verix. Real Intent and Co-Design Automation jointly developed the DAS and donated it to Accellera this year. This jointly developed and donated spec is the basis for the SystemVerilog Assertion Language.
Mentor Graphics also announced support for SystemVerilog and plans to incorporate the new standard into a range of its tools, with availability beginning in 2003. Mentor's Model Technology division is adding support for SystemVerilog to its ModelSim mixed-language simulator.
Tera Systems, Inc. introduced TeraForm-RTL Design Consultant, a design analysis tool that promises to improve the quality of RTL code prior to design implementation. Using the tool, SoC designers and ASIC vendors can detect and correct errors early in the design process, thereby shortening the overall design cycle and streamlining the RTL handoff step for design implementation, the company said.
TeraForm-RDC directly addresses the need for cross-domain knowledge by encapsulating the knowledge of both expert RTL-designers and physical implementation specialists in a reusable form. TeraForm-RDC's physical modeling at the RT level allows system engineers to interactively explore and debug their entire design, not just individual RTL blocks. The tool can check the RTL for semantics, timing, area, congestion, synthesis constraints, and layout implementation-related issues prior to passing the design to the next implementation step. At each step of the design flow, the tool not only reduces future iteration steps, but also provides invaluable RTL links to the cause of the error, greatly
accelerating design debug.
The company also noted that TeraForm-RDC returns predictability to the design flow by providing the missing communications channel at every level of design handoff, ensuring that block level designs integrate into the chip, that the chip level design is acceptable for layout and that the final design passes vendor specific handoff criteria. At each stage, it reduces iterations and allows problems to be corrected early at the RT level.
EDA newcomer Novilit, Inc. launched AnyWare, its next-generation development environment meant to accelerate the design cycle for embedded communications protocols. With the introduction of AnyWare, Novilit believes it is advancing EDA technology for better development and integration of embedded communications hardware, firmware and software.
AnyWare addresses a trend in the communications industry -- the need for higher processing speeds, along with the need for communications protocols implemented in hardware rather than just software. AnyWare shortens design cycles, enables reusability and reduces costs and can be used to target a variety of implementation platforms, including ASICs, FPGAs, network processing units, and general-purpose processors.
AnyWare automatically generates a fully portable protocol stack that can produce output in a variety of different formats. It can be used to implement protocols for any network device or product, at any point within the system -- in a CPU, NPU, or DSP. It can be used to instantiate protocols in ASICs or programmable devices such as FPGAs. AnyWare encompasses a suite of embedded protocol development tools. It has four main components -- a protocol definition language, a 40-stage compiler, a code editor, and a test and debug environment.
Esterel Technologies developed a new methodology for automating the generation of a top-level validation test suite for SoC designs. The methodology, when used with Esterel Studio 4.0, speeds the validation of design block and CPU core integration by relying on transactional models that describe blocks according to their services (such as read/write) rather than their individual signals.
STMicroelectronics will be the first customer to have taped out a design after applying top-level validation. The chip is a new multiple-block design for the digital consumer market. Using Esterel Studio 4.0 and the top-level validation methodology, STMicroelectronics generated more than 1,200 test cases for their new SoCs in a week. Using hand coding, fewer than 10 test cases could have been generated in the same period. As a result of this new methodology, STMicroelectronics will be able to tape out its new SoC with a high degree of confidence that design block and CPU core interaction has been thoroughly validated, Esterel said.
inSilicon Corp. reported that Agilent Technologies has signed an agreement for inSilicon to supply USB 2.0 PHY IP to Agilent's Semiconductor Products Group. Certified by the USB Implementer's Forum, inSilicon's USB 2 PHY is a mixed-signal semiconductor IP solution designed for single-chip Hi-Speed USB 2.0 integration in both device and host applications. The USB 2 PHY integrates high-speed, mixed-signal, custom CMOS circuitry in compliance with the industry-standard UTMI Specification. USB 2 PHY technology supports the USB 2.0 480-Mbps protocol and data rate, and is backward compatible with the USB 1.1 legacy protocol at 1.5 and 12 Mbps.
Altera Corp. said it is now shipping its fast Fourier transform (FFT) MegaCore function, optimized for the Stratix device family. The new FFT version 1.3.0 IP core is more than twice as fast as previous versions and consumes 50 percent fewer logic elements (LEs) when implemented in Stratix devices. These improvements were achieved by taking advantage of the DSP blocks in the Stratix architecture, including embedded multipliers, adders, subtractors, accumulators, and pipeline registers, Altera said.
The Stratix DSP blocks are used to achieve high data throughput required for computationally demanding applications, providing a combined throughput of up to 56 giga multiply accumulate operations per second (GMACs) -- more than 10 times the rate available today from leading, standalone DSPs.
InTime Software announced that AMCC has purchased Time Architect, Time Planner and Time Builder for pre-RTL, RTL and gate-level floorplanning. AMCC designs, develops, manufactures, and markets high-performance, high-bandwidth silicon solutions empowering intelligent optical networks.
SynTest Technologies, Inc. announced TurboDebug-SOC/Memory, the second member of its Design for Debug/Diagnosis (DFD) product line. TurboDebug-SOC/Memory reduces the cost of test and debug for SOCs with large BISTed embedded memories. TurboDebug-SOC/Memory debugs and diagnoses failures on large embedded memories. It tests and debugs BISTed embedded SRAM/ROM memory on ASICs/SOCs. It enables users to detect memory failures down to the bit level. The testing and diagnosis is easy to perform using pull-down menus. Error types and locations of the errors are displayed on the PC screen.
Zenasis Technologies, Inc., extended its second round of financing, accepting $2.0 million from VentureTech Alliance, the Taiwan Semiconductor Manufacturing Company Ltd. affiliated venture fund, and Selby Venture Partners. Funds will be used as working capital to expand the Zenasis R&D efforts. The additional second round investments by VentureTech and Selby brings the total amount raised to $9.5 million since Zenasis was founded in 2000.
Celestry Design Technologies, Inc. announced that Goyatek Technology, Inc. has selected ClockWise Celestry's clock tree synthesis product for its 0.18-micron and below design flow. Celestry said ClockWise helps customers achieve better silicon performance in hours rather than weeks with its skew and clock tree synthesis technology.
According to Tony Peng, Goya vice president, the ClockWise tool helped tapeout multiple designs that can't be handled by other products. The existing tree optimization feature in ClockWise was superb in performing both pre-route and post-route skew optimization, he said. In one design with almost 15,000 leaves, ClockWise optimized the post-route clock skew from 0.7ns to 0.3ns to achieve our design timing criteria.
Celestry also reported that Tower Semiconductor has selected Celestry's device-model parameter extraction products and characterization services for Tower's 0.18-micron process and new Fab-2 technologies. In addition, Celestry is providing Tower with a variety of analog device models for its submicron designs. Tower said it chose Celestry's device-model development product BSIMPro+ for device-model extraction and Celestry Labs services for process characterization. Tower said it will utilize Celestry Labs' modeling and characterization services for device development and fast prototyping and Celestry's BSIMPro+ to enhance its model self-extraction capabilities.
Electronics Workbench announced a new customer support service for the company's professional-level customers. Electronics Workbench brings together its product and service-related elements into the customer support program called Connexts. Early customer deployment of Connexts reveals that Electronics Workbench is able to respond to and solve a customer's advanced design problems significantly faster and with better accuracy than with traditional phone and email methods.
Connexts extends the boundaries of traditional technical support to the next level -- collaborative visualization. By utilizing the technology of the Internet Design Sharing option bundled with every professional-level version of the company's Multisim tool, both the technical support engineer and the customer are able to simultaneously view a design in real time, on-line. Design problems can be pinpointed immediately; clarity is absolute, leaving no margin for error or misinterpretation.
Sonics, Inc. and Denali Software, Inc. announced a business and product partnership to co-market their respective IP cores as a complete solution. The alliance creates the first open core protocol (OCP) -compliant memory system that integrates Denali's Databahn memory controller with Sonics' MemMax memory scheduler and SiliconBackplane MicroNetwork smart interconnect IP.
The joint Sonics-Denali memory system guarantees initiator cores both bandwidth and quality of service to off-chip DRAM. Efficient utilization of memory bandwidth gives SOC designers the freedom to choose the most cost-effective DRAM for their particular applications. This solution satisfies a wide range of memory system requirements and supports “plug and play” integration through compliance with the OCP interface standard. The pairing of Sonics' SMART IP and Denali's advanced memory controller cores provides configurability and support for multithreaded tasks, in addition to removing the routing congestion problems that typically occur with proprietary memory system
Synplicity, Inc. announced Canon, Inc. has used the Synplify ASIC synthesis software to tape out a complex SoC design. Canon has received confirmation of tape out success from its ASIC partner, Fujitsu Limited, for a two-million-gate, 0.18-micron image processing design. Using the high-productivity Synplify ASIC software, Canon said it was able to quickly achieve better timing and area results without extensive RTL re-coding, resulting in reduced power consumption, cost and turnaround time.
eInfochips and Verisity Ltd. announced that Integrated Device Technology, Inc.(IDT) selected eInfochips' PCI-X e Verification Component (eVC) to be used in their Specman Elite verification environment. eVCs are reusable plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. IDT said it chose the PCI-X eVC to cut the time it takes to create their verification environment and ensure a higher-quality design.
Altera Corp. and Mentor Graphics announced that Altera's Quartus II design software and the Mentor Graphics Precision Synthesis software will support the Synopsys Design Constraint (SDC) format that is widely used to define ASIC design constraints when using tools from multiple vendors. Upcoming releases of the Precision Synthesis and Quartus II design software will read and write the SDC format, saving designers valuable time otherwise lost to reentering and debugging constraints when moving among different vendor tool suites, the companies said.
Altera also reported that along with Synplicity, Inc., it has introduced a new standard interface called Physical Synthesis Design Format (PSDF) that increases interoperability between physical synthesis and place-and-route tools. This new Altera interface, which was co-developed with Synplicity, allows for improved timing and placement information for use by physical synthesis tools. As a result of this interface, circuit performance is significantly improved while the number of design iterations is reduced when using Synplicity's Amplify Physical Optimizer software and Altera's Quartus II design software.
AXYS Design Automation, Inc. said that Matsushita Electric Industrial Co., Ltd. has licensed AXYS Design's MaxSim and MaxCore Developer Suites to create fast and accurate simulation models that can be used for early embedded software development for its complex SoC designs. AXYS Design will supply its development tool suites to Matsushita Electric's processor and architecture development teams.
Adelante Technologies and AXYS Design Automation announced the development of a virtual prototype of Adelante's JPEG2000 reference platform, which includes Adelante's Saturn DSP Core, an ARM920T core, and Adelante's highly optimized Wavelet and Ebcot co-processors. This reference platform is implemented in AXYS Design's MaxSim prototyping environment and enables designers to do early-stage software development and debugging of system software, and evaluate system-level hardware/software trade-offs.
Tensilica, Inc. announced immediate availability of the Mentor Graphics XRAY Debugger for Tensilica's Xtensa IV processor core. The tool provides a comprehensive debug environment for the thousands of unique processor configurations that are possible using Tensilica's Xtensa processor architecture, the companies said. Using the XRAY Debugger, designers can simultaneously verify and debug the application and system software running on one or more Xtensa cores in their embedded SOC designs, as well as other industry-standard cores supported by the XRAY debugger environment.
Tensilica, Inc. also announced that the corporate R&D center of Olympus Optical Co., Ltd. has licensed Xtensa technology. Olympus initiated research earlier to determine Tensilica's applicability in its product lines, and found a variety of possible uses in advanced embedded applications.
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-- Ann Steffora, EDACafe.com Contributing Editor.