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October 04, 2004
Memory Continued
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Last week's editorial was on Memory. That article covered the different types of memory, emerging memory technologies, the market for memory and the leading vendors in this market space. Most industry analysts expect the amount of embedded memory used on a chip to continue to grow dramatically in the next few years, from consuming more than 50% of the die area today to 70% by 2005, and up to 90% by 2011. This strong growth is being driven by an increase in the development of integrated applications such as consumer electronics that combine voice, data and multimedia on one SoC.

The following is an excerpt from Virage Logic's 10K filing with the SEC.

“The demand for high-performance computing and communications applications and the availability of increased bandwidth for Internet applications has made memory an increasingly critical element of the overall operation of SoCs used for these applications. Historically, integrated circuit designs were dominated by the logic function, while memory storage was usually provided in external devices. In order to achieve increased speeds, chip designs now require closer physical proximity and better integration between the logic and memory functions and require more customized memory functions. The need for this proximity, as well as advances in semiconductor technology and the ability to
customize the size and configuration of memory functions within a SoC, is creating increased demand for embedded memory. It is now common for a SoC to contain many memories with different functions configured in different sizes and shapes to optimize the area and functionality of the chip. We estimate that memory functions typically comprise between 30-50% of the chip area in a SoC design and believe that this percentage will increase with the growth of memory-intensive applications.”

The paragraphs that follow cover several companies whose offerings address this situation.

Denali Software Inc a privately held company was incorporated in 1996 and today has about 100 employees. Denali provides EDA tools and semiconductor IP solutions for chip interface design and verification. The firm publishes the Denali Memory Report (DMR), a monthly publication that contains trends, analysis, and news for the semiconductor memory industry. They also sponsor the MemCom conference series for semiconductor memory and PCI Express technology.

Very early in its existence Denali created the XML-based SOMA (Specification Of Memory Architecture) language to capture all the unique characteristics -- timing, features, and functionality -- of any particular memory. Working with every major worldwide memory vendor, Denali has characterized all commercially available memory product offerings as well as unannounced products in SOMA files. Currently over 8,000 SOMA models are made available on memory vendor websites and Denali's own

The online database at eMemory.com provides instant access to SOMA files covering over 20 memory types (categories = DRAM, SRAM, Non-volatile, CARD Memory and Embedded/FPGA) from over 40 vendors. An intuitive interface makes it easy to search for SOMA files based on: Vendor, Memory Type, Data Width, Size and/or Part Number. A search with the inputs: vendor=ELPIDA; class=DDRII_SRAM; and Data Width=All Widths yielded 15 matches. The component details for one match were:

Part Number: EDE5104AB-4A
Vendor: ELPIDA
Class: DDR_II
Configuration: 512Mb(32M x 4bit x 4bank)
Description: 512Mb DDR_II SDRAM
Maximum Frequency: 200 MHz @ CL=5,3,4

At this point one can request the SOMA model for this device to be downloaded. The version of MMAV required is also identified (3.000-0071 or greater). Existing customer can download this software for their target computer environment, if necessary. Users also have the option to download memory-controllers for the device. Here it is necessary to answer the following questions: What are your data throughput requirements (Gb/sec)? What is the speed of your memory bus (MHz)? What memory devices are you targeting? and What is your target ASIC process (µm)?

Denali offers its MMAV (Memory Modeler - Advanced Verification) verification IP for memory simulation and system verification. MMAV enables users to observe and operate on system-level data transactions during simulation. This "data-driven verification" approach is the key to optimizing regressions and accelerating the overall verification process.

The generic functionality of the various memory architectures are captured in a set of highly-optimized 'C' models. The vendor-specific features and timing for any particular memory device are defined within a SOMA file. Once the MMAV model objects are linked into the simulation environment, modeling any type of memory is as simple as referencing the appropriate SOMA file for that particular memory device. MMAV automatically monitors all the timing and protocol requirements specified by the memory vendor. The MMAV model objects are integrated to all popular simulation/verification environments (Verilog, VHDL, C-based, HW/SW Co-simulation and Testbench).

At a very basic level, MMAV provides direct access to memory through commands that enables users to read, write, save, preload, and compare memory contents at any time during simulation. For data-driven verification, MMAV provides robust assertions to catch erroneous data transactions and difficult bugs associated with: uninitialized memory accesses, redundant reads, and data overwrites. These powerful assertions can trigger breakpoints to catch bad data transactions as they happen, not thousands of cycles later when/if the erroneous condition propagates data to an observable output.

A built-in address manager makes it easy to assemble any number of discrete memory components to form a contiguous memory address space, or "system memory". Any of the memory commands or assertions can then be applied to system memory. Other application-specific data structures include linked-lists and mirrored memory arrays.

MMAV supports PureView, a debugging tool that enables users to view and edit memory contents interactively, or during post-simulation analysis. PureView provides concise memory transaction data in the form of a history window which displays the transaction history for the device, or all transactions associated with a specific memory location. PureView also accelerates waveform level debugging with popular tools such as Novas Debussy where the tools enable
synchronized views of waveform information, memory data, and memory transaction for advanced debugging.

Denali's Databahn product provides a way to configure the optimal memory controller core for a design, validate the performance within the context of the system, and implement the solution in Silicon. The entire process is managed by an online application infrastructure, and a browser-based interface gives complete visibility and control over each step of the process:

In addition to configuring a Databahn controller online, users can instantly initiate a simulation of the actual configured RTL using generic stimulus, or they may upload the memory access profile for their specific application. The simulation results are automatically analyzed and formatted into an online performance analysis report along with the associated VCD waveform files. If the configuration meets the requirements, the synthesizable RTL can be made available for download along with sample testbenches, register settings, synthesis scripts, and layout guidelines. Quality is assured through a robust verification suite and the rules-based configuration manager.

Databahn has over 100 design-wins and 45 chips in production. The XML-based SOMA format has also been extended to support the comprehensive memory subsystem parameterizations associated with the Databahn configurable memory processors.


In July 2002 Synopsys announced a full line of memory IP which includes memory models, memory controllers, and memory BIST. The memory solution, as part of the DesignWare IP Library is available to designers through a single license and price, with no per-use fees or royalty payments. There are thousands of pre-verified simulation models of memory devices from over 30 memory vendors. The models integrate with simulators through the industry de facto standard SWIFT interface, which is supported by all Synopsys simulators and by all other major simulator vendors The Memory Controller MacroCell is a fully configurable, synthesizable solution for both dynamic and static memories. A single
controller can support multiple memory types such as DDR-SDRAM, SDR-SDRAM, SSRAM, SRAM, SyncFlash, Flash and ROM devices. The Memory Controller contains interfaces to the system via an AMBA AHB 2.0 compatible interface and could also be interfaced to other buses through a simple gasket. Memory BIST MacroCell, is a configurable, fully synthesizable solution for memory built-in self test of embedded SRAM memory structures. DesignWare Memory Building Blocks are technology-independent, high-performance, flip flop or latched based storage elements such as embedded SRAMs, FIFO, FIFO Controller and Stack. DesignWare Memory Building Block components support the complete Synopsys design flow
including synthesis, static timing analysis and formal verification.

Synopsys had announced an agreement to acquire MoSys, a provider of memory IP, for $432 million in stock and cash but later terminated the agreement. Analysts criticized the price (~2 MoSys' market capitalization).

Rambus, Inc.

In the mid nineties Intel sought out a memory technology that could provide sufficient bandwidth headroom to give them four to five years of chipset stability. Intel chose Rambus that had been achieving some success with the adoption of their technology in games consoles such as Ninetendo. In November 1996, Rambus entered into a development and license contract with Intel. The contract provided for the parties to cooperate in the development of a specification for Direct Rambus next-generation 64 Mbit RDRAMs to be targeted at the PC main memory market segment. The contract also called for Intel to use reasonable best efforts to develop a PC main memory controller designed for use with these
RDRAMs. The contract had licensing fees, royalties, reverse royalties, stock warrants and a commitment from Intel to use its best efforts in marketing, public relations, and engineering to make the Rambus-D DRAM the primary DRAM for PC main memory applications. Intel also made investments in some memory manufactures to assist in the cost of supporting RDRAM. With this leverage Rambus was able to secure licenses from DRAM manufacturers which collectively accounted for over 90% of worldwide DRAM sales at the time. Rambus had its IPO in May 1997. Several memory manufactures complained about what they saw as excessive royalties. This situation led to a number of patent suits, counter
suits and investigation by FTC that are still in play today.

Rambus has three memory interface products: the relatively mature RDRAM and the more recent DDR and XDR DRAM. The RDRAM interfaces have been implemented in RDRAM memory devices, controllers, processors and chipsets in tens of millions of consumer, computing and networking systems and products. The DDR interface solution provides a comprehensive suite of interface cells and services, supporting mainstream DDR1/2 up to 800MHz data rates and graphics DDR, including GDDR1/2/3 up to 1600MHz data rates. The XDR memory interface provides a quantum leap in performance. XDR (eXtreme Data Rate) DRAM data rates from 3.2 to 6.4GHz are achieved for next-generation graphics-intensive consumer/computing,
high performance main memory and networking applications.

The XDR memory system solution consists of five primary elements: DRAM, IO Cell (XIO), Memory Controller (XMC), Interconnect and Clock Generator (XCG). The XDR DRAM is a memory component offered by Rambus memory partners that contains a compliant XDR DRAM interface and a standard DRAM memory core. Compliant DRAM components may vary in such features as memory density, page size, core speed grade, and data bus width. The XCG produces low noise, low jitter differential clock signals for the memory system and is available from Rambus clocking partners. XDR consists of three physical layer building blocks: Rambus' FlexPhase, a controller based circuit technology; differential Rambus signaling
levels (DRSL): and octal data rate signaling. FlexPhase allows for a very precise centering of data with on-chip clock without having to trace length match signals. DRSL is a very high-speed low power signaling interface for scalable high speed point to point bi-directional differential data signals. Octal data rate signaling allows 8 bits to be transmitted per clock cycle, which allows XDR to achieve a 256Mbit device at 3.2GHz data rates with a 400MHz clock.

Rambus also offers a multimode XDR/DDR controller interface capable of attaching to DDR or XDR DRAM on the same cell. This provides greater flexibility and lower investment as a single solution can support multiple offerings.

In January 2003 Rambus announced multi-year licensing with Sony, Sony Computer Entertainment and Toshiba for its high speed interfaces. In late December 2003 Toshiba Corporation announced that it had started to sample 512-megabit XDR DRAMs with a data transfer speed of 3.2GHz. On July 19, 2004 Rambus announced that that Matsushita Electric Industrial Co, aka Panasonic, had selected its DDR2 and XDR memory interfaces. At the Intel Developer Forum in September Rambus held a live demonstration of its Dynamic Point-to-Point (DPP) technology applied to an XDR memory system.

I spoke with Rich Warmke, Rambus' Product Director of Memory Interface. He stressed that Rambus delivers its memory interface as a complete, drop-in macro-cell instead of a do-it-yourself kit of technology building blocks, such as I/O pads and delay lock loops (DLLs), requiring engineers to assemble, integrate and verify on their own. Rambus also provides engineering services such as package design, system board layout, reference guidelines, and bring-up support to ensure that the memory interfaces work in the application environment. This complete approach to interface cells provides customers with improved time-to-market, lower design risk, higher performance, and lower total cost.
Rich believes that Rambus value proposition will continue to win more advocates as memory performance pushes the envelope.

He explained that customers choose Rambus because a) they are unsure that they can get to high volume production quickly enough, b) they prefer to use their technical resources on other opportunities or c) they lack sufficient system level expertise (packaging, PCB, multiple DRAM vendors).

I asked about flash memory. He said that that Rambus had no specific products for flash memory. The speed of the interface is not high enough so that potential customers would be concerned about implementing their designs. I asked about the possible impact of new and emerging memory technologies. He does not expect any of these to dislodge DRAM in the near term. Rambus will focus on the interface not the storage mechanism. If some technology were to grab a foothold, customers would come to Rambus to develop the interface. He sees the transition to DDR2 having the largest impact. This has started with PC main memory but there will be ripple effects and other market segments will
follow. He believes that the single ended signaling of DR1/2 and GDR1/2 will run of gas compared to XDR differential signaling. Differential signaling enjoys higher common mode noise rejection characteristics than single-ended signaling and differential input receivers are able to receive much smaller signal swings significantly reducing power, cross-talk, and EMR

Publicly traded memory IP providers

For months I have co-authored on this website quarterly financial analyses of eight IP companies, several of whom have offerings in the memory arena. These include Artisan, Mosys, Rambus and Virage Logic.


Artisan Components, Inc. is a leading provider of physical IP components for the design and manufacture of complex system-on-a-chip integrated circuits. The company incorporated in California in April 1991 as VLSI Libraries Incorporated, changed its name to Artisan Components, Inc. in March 1997 and reincorporated in Delaware in January 1998. The company's comprehensive product portfolio includes digital, analog and mixed-signal IP. Artisan offers embedded memories, standard cells, I/Os for general-purpose and specialty applications and system interface PHYs.
Artisan has licensed its IP components to over 1,200 companies involved in integrated circuit design. The company's revenue for the fiscal year ended September 30, 2003 was $68.5 million. In fiscal 2003, IBM accounted for 18% of total revenue, TSMC accounted for 17% of total revenue and Chartered accounted for 10% of total revenue.

Artisan offers three memory families: High-speed, high-density, and low-power. High speed is achieved through a combination of proprietary design innovations that include latch-based sense amplifiers, high-speed row select technology, precise core cell balancing and rapid recovery bitlines. Low power is achieved through a combination of proprietary design innovations that include latch-based sense amplifiers, a power efficient banked memory architecture, precise core cell balancing and unique address decoder and driver circuitry.

Embedded memory components include single- and dual-port random access memories, read only memories and register files. Embedded memory components are configurable and vary in size to meet the customer's specification. Memory components include features such as a power down mode, low voltage data retention and fully static operation. In addition, memory components may include built-in test interfaces that support popular test methodologies. An additional feature, FlexRepair, includes redundant storage elements to allow the implementation of repair capabilities with existing embedded memory architectures which may help increase the manufacturing yield. The logic for testing, repairing,
and replacement of faulty bits is implemented in the standard cell portion of the chip.

Artisan describes its approach to IP licensing, termed the Foundry Library Program, as follows. Artisan has licensed and distributed its intellectual property components to over 15 companies involved in the manufacture of integrated circuits who have agreed to pay an upfront license fee and also agree to make future royalty payments. For most of the firm's IC manufacturing customers, the company distributes and licenses its IP components to companies that design integrated circuits. While the basic elements of memory, standard cell and input/output components are distributed to design companies at no charge, design companies pay a direct license and support fee to receive analog,
mixed-signal and other customized components and support. As part of the license agreement, the design companies agree to manufacture any integrated circuit design using any of the IP components at the particular integrated circuit manufacturer for which Artisan has developed them. The IC manufacturer then generally pays a royalty. Artisan has licensed and distributed IP components at no charge to over a thousand companies involved in integrated circuit design. Over 100 of these design companies have paid direct license or support.

Artisan's Process-Perfect Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. Each product is delivered with a complete set of views and models for leading EDA tools.

On August 23, 2004 ARM Holdings plc announced a definitive agreement under which ARM will acquire Artisan in a cash and stock deal for an aggregate consideration of approximately $913 million, a 42% premium. ARM, a British company, is a provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals, and system-on-chip designs to leading international electronics companies.

Monolithic System Technology, Inc (MoSys)

MoSys was founded in September 1991. The company developed an innovative embedded-memory technology, called 1T-SRAM. In 1998 MoSys started shipping high speed SRAM stand-alone memories based on this technology. In the fourth quarter of 1998, the firm changed the emphasis of its business model to focus primarily on the licensing of its 1T-SRAM technology to semiconductor companies and electronic products manufacturers. One of the early licensees was Nintendo for its GameBoy video game consoles. The firm had its IPO in 2001. Cumulative chip sales by its licensees exceed 80 million.

For fiscal year 2003, net revenue was $19.2 million compared to the $27.8 million reported in fiscal 2002. Net income in 2003 was $2.5 million, compared to net income of $12.4 million reported in 2002. Licensing revenue which consists of fees paid for engineering development and engineering support services was 38% of total revenue in the most recent quarter. Royalty revenues which are earned when licensees manufacture or sell products accounted for 42% of revenue in the last quarter. The company has signed license agreements related with 45 companies, 12 of which have paid royalties to date.

In February 2004 Synopsys announced an agreement to acquire MoSys in a transaction valued at ~$346 million net of cash. In April Synopsys terminated the merger and MoSys sued to force completion of the merger. In July MoSys and Synopsys announced the settlement of litigation relating to the termination. MoSys received $10 million in termination fees.

The 1T-SRAM has a 1transistor/1capacitor bit cell structure compared to the conventional 6 transistor SRAM memory storage cell. Consequently, the 1T-SRAM requires 50% to 70% less silicon area and 70% less cost. It also has higher yield percentage and lower power consumption. 1T-SRAM technology options include mobile, extended reliability and extended density. 1T-SRAM is actually based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the 1T-SRAM unique is that it offers a true SRAM-style interface that hides all refresh operations from the memory controller with a combination of raw speed and
clever design. Precharging takes place during every access, overlapped with the end of the cycle and the decoding portion of the next cycle. The speed comes from the use of many small banks. MoSys provides a separate refresh controller for every bank. At the end of 2002 the company introduced 1T-SRAM-Q (Quad Density) technology doubling the density of 1T-SRAM memory. This utilizes the patented Folded Advanced Capacitor technology.

Virage Logic Corporation

Virage was founded in 1996. The company provides embedded memory semiconductor IP in predetermined shapes, sizes and types that can be incorporated by semiconductor designers into their SoC designs and embedded memory compilers that allows semiconductor designers to configure memories to the desired specifications for their SoC designs. In 2003 the company had revenues of $40 million.

Virage Logic's IP consists of (1) embedded memories, (2) compilers that allow chip designers to configure its memories into different sizes and shapes on a single silicon chip, (3) memory test processor and fuse box components for embedded test and repair of defective memory cells, (4) software development tools that can be used to build memory compilers, (5) logic elements, and (6) I/Os. The firm also provides custom design services. Customers include fabless semiconductor companies and integrated device manufacturers.

Virage Logic has architected three separate families of sub-megabit embedded memory compilers under the Area, Speed, and Power (ASAP) Memory product line. The High-Density (HD) memories address the needs of many applications that are optimized for area; the High-Speed (HS) memories address the requirements of high-performance systems; and the Ultra-Low Power (ULP) memories address the needs of power-sensitive portable applications. All ASAP memories can optionally include the comprehensive Built-In-Self-Test (BIST) implementation found in Virage Logic's STAR Memory System, or integrate with most third-party BIST engines. The ASAP memory product line is available in many different memory
types including single- or dual-port register file, single- or dual-port SRAM, synchronous or asynchronous SRAM and ROM.

Virage Logic's Self-Test and Repair (STAR) Memory System includes an integrated test and repair capability that enables our customers to achieve higher yields of semiconductors. The system includes one or more STAR SRAM memory blocks, a STAR Processor and a STAR Fuse Box. The STAR SRAM comes with redundant locations, the STAR Processor decides how to test and repair defective SRAMs and the STAR Fuse Box stores the repair information.

NetCAM, Virage Logic's content-addressable memory (CAM) compiler, can be used in SoCs that are found in routers, switches and other high-bandwidth Internet infrastructure equipment to accelerate hardware-based searches.

Weekly Headlines

At FSA Design Modeling Workshop OEA International Invites You to Attend Presentation on 65nm and 90nm Interconnect Modeling Challenges

Nassda Moderates Crosstalk Panel at Fabless Semiconductor Association Technical Conference

Mentor Graphics Announces Call for Papers for User2User 2005

Renesas Technology Standardizes on Cadence MaskCompose to Reduce Mask-Making Cycle Times and Costs; Tool Speeds Time-to-Market for 90 Nanometer Designs

Altium Japan announces distribution agreement with Memec Japan

Cimmetry Released AutoVue 18 For UNIX

Synopsys' Design Compiler FPGA and Xilinx Virtex-4 FPGAs Target Complex ASIC Prototype Applications

ChipX Selects SynTest's VirtualScan -- Scan/ATPG Tool to Reduce Test Costs for Next Generation Large ASICs

HP Workstations To Shift From Itanium

Accellera Sponsors & Presents at GSPx Conference; Open Meeting Offers SystemVerilog & PSL Updates, Assertion-Based Design & IP Integration Panel

Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models

Celoxica Announces Design and Synthesis Support for Xilinx Virtex-4 Domain Optimized FPGAs

AccelChip Inc. Enhances Interoperability by Joining the Mentor Graphics OpenDoor Program

Fairchild Semiconductor's USB 2.0 Transceivers Offer Industry-Leading 15kV ESD Protection in Ultra-Small Packaging

TI Introduces Industry's First Multipoint-LVDS Line Drivers for Clock Distribution

National Semiconductor Introduces the Industry's Highest Power Density Thin SOT23 Buck Switching Regulators

Cypress MicroSystems' Powerful New PSoC Enhances Integrated Systems Control

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