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August 11, 2003
More on Object-Oriented Design
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

As an editor, it is always fun/informative to receive letters from readers. The article in the July 28th issue of EDA Weekly, The Root of All Evil, precipitated a lengthy Letter to the Editor posted in the August 4th issue. The August 4th Letter to the Editor then precipitated the two letters posted here.

I am grateful to Mark Jones for the initial conversation detailed in the July 28th issue, to Seth Goodman for his August 4th Letter to the Editor, and to Sy Wong and Kevin Dewar for their additional contributions to the dialog on object-oriented design. These letters have been slightly edited, but are pretty much printed as received.

Letter No. 1 - August 8, 2003

Hi Peggy

Another 'Letter to the Editor' on the evil/wonderful nature of objects...

It's always stimulating to see reader responses to articles and interviews, and there was probably a lot in Mr. Jones' article that might have prompted both agreement and disagreement, but the reply by Mr. Goodman seemed curiously overwrought, although at least he didn't sit on the fence.

Mr. Goodman has picked on the area of Object-Oriented Design, as used in software engineering, to arrive at the conclusion/remonstration that "we should not seriously consider any system that looks even remotely like OO design."

Phew! Not scared to be both prescriptive *and* blinkered.

The justification for this firm advice seems to be that OOD is an unmitigated disaster in the software world and shouldn't really be tolerated there, let alone let loose into the hardware domain. However, whilst many people undoubtedly do consider OO SW rather inefficient, and many more take issue with Microsoft's market influence, it seems unarguable that OO design has actually met with widespread acceptance in industry. The people using it are intelligent professionals, many of them are hugely experienced, and they would not have chosen it unless they thought it the best choice available (although not necessarily an ideal choice of course).

I think that Mr. Goodman has exaggerated the actual inefficiency of real SW systems developed with OOD. Whilst there may be some systems that have "several orders of magnitude" less performance than they could have, I don't believe that this level of inefficiency (i.e. thousands of times) is typical of either mainstream OOD systems or any reasonably competently designed ones. Certainly it is patently unfair to say that hardware improvements have merely allowed us to stand still as the software bloated. A 2003 mainstream PC may have a cost similar (or actually less in real terms) to one from 1990, but I don't think that many people would consider them to be functionally equivalent to the user.

Additionally, Mr. Jones mentioned other examples of software using OOD and, as one of these was Linux, it couldn't be said that OOD is entirely the result of Microsoft marketing. The Java language is another OO example that has clearly gained widespread (or pervasive) acceptance without anyone yet being able to blame it upon academics (many of whom must be surprised to learn of the apparent level of influence that they have).

We need to remember why abstraction is sought after in the first place and I think there are two, closely related reasons.

Firstly, the availability of higher abstraction levels allows a greater choice of trade-off points between design effort/cost and system performance. When a software product can be developed in half the time/cost, it will sometimes be perfectly acceptable to allow it to have half the performance. (I certainly don't notice if my phone takes 50ms or 100ms to recognize an incoming call.)

Secondly, as systems get more complex, there comes a point at which it isn't even an option to use a low-abstraction methodology, whatever the likely performance gain theoretically achievable, since it could never realistically be completed. At this point (which some would argue has already been reached in many systems) it is instructive to compare an OOD system's "low" performance against that of a system that can't be designed at all (performance = zero).

In chip design, we can similarly see that whatever loss of performance occurred as the industry went from transistor-level full-custom optimization to standard-cell based schematic entry to HDL/synthesis, the difference is immaterial to somebody designing a 10 million gate ASIC since they aren't going to use anything other than RTL, IP, and compiled blocks. As gate-counts continue to rise then abstraction levels will have to rise with them and perhaps it is a little premature to state that nothing can be learnt from abstraction techniques widely practiced in another important engineering discipline.

I also believe that the reason Hardware seems to contain fewer (product) bugs is not because the *design* methodologies are inherently better than Software, but is a result of more effort being put into verification at an earlier point in the product cycle (since multiple ASIC re-spins are ruinous). In terms of number of defects/KLOC, my experience has been that there isn't much difference between hardware designers writing RTL and software designers writing high-level languages, at the point of initial coding. Hardware designers may get these defects out more quickly, but this is mainly a result of economic necessity although the effort required to achieve this is rapidly getting out of control. One attribute of a good design methodology (for software, hardware, or systems) is that it would allow fewer defects to get into design and allow the ones that did get in to be more easily found and fixed.

It is interesting that one of the major other approaches to enhancing hardware design efficiency is pervasive re-use of IP. This approach is itself really a simple type of "object-based" design in which the more successful IP blocks will have to be reasonably general and flexible - i.e. "inefficient" compared to fully optimized custom solutions.

Mr. Goodman mentions that other, more efficient, methods of abstraction do exist and I would be genuinely interested to hear what he believes these are, and to have the opportunity to perhaps compare what they have to offer for chip design against the ideas from Mr. Jones.


Kevin Dewar
MCD Design Consulting

Letter No. 2 - August 5, 2003


A computer is a real object, which in turn is built up from a hierarchy of increasingly complex real objects, whether on a PC board or inside an IC. With hardware designed with software, the concept of objects is indistinguishable whether as software or hardware, if the design language in either [paradigm] is unified into one.

In his letter in the August 4th issue of EDA Weekly, Mr. Goodman mistakenly blames object-oriented programming when he says, 'The object-oriented approach is indeed incredibly wasteful of processor and memory resources.'

The real culprits are the increasingly bloated multi-tasking operating systems (MTOS) such as Windows or Linux (a.k.a. UNIX). The computer science community was brought up on UNIX and C after Bell Labs gave the code to universities for free. Were it not for supporting MTOS like the Pentium and the PCI bus, a processor could be made for almost nothing today. Why make a processor faster and faster and memories bigger and bigger only to chop them up for multiple tasks?

Meanwhile, you can wake up the IC design community with an editorial citing the major mistake made by VHSIC in 1980 at Woods Hole that declared the then DoD-mandated Ada language was inadequate for use as an HDL. That was at a time when a practical Ada compiler was not available. Obviously, the Ada inadequacy conclusion was not based on factual tests. The resulting VHDL is a hodge-podge of copied Ada constructs, plus unnecessary additions that are also convoluted. Now IC designers are slaves to the IEEE HDLs and the necessary EDA tools.

Ironically, Ada was initiated by [Donald] Rumsfeld in 1975 to unify the many languages used by weapons systems. However, Ada was buried by too many bureaucrats [who were not] actual software developers. The "parallel or concurrent" construct that [gave] Ada a reputation for being too large and too complex was the same evil time-sharing concept of MTOS. It is impossible to have parallel processing on a single threaded computer, only pseudo or virtual concurrency. Most of the guts of a Pentium go to support the MTOS, to make it go faster in order to cut up time for sharing between tasks.

For 10 years, I had proved the VHSIC 1980 declaration wrong. Ada has a package construct that provides a clean interface called Specification and a Body with implementation. The Body can use Boolean expressions as system-level implementations or as connected library cells. Both should be logically identical. Syntactical and semantic errors are caught by the compiler, and validated by an official test set. Being a programming language, the designer can ascertain functional correctness by writing a test program. Since the implementation is hidden from the test program, transition between Boolean implementation and connected cells need only relinking to run the test again.

I use a compiler by a small company in Wisconsin, running on a decade old 486 PC with DOS, which does most compilations in a couple of seconds or less. That supports the slow downs due to MTOS. It is certainly cheaper than 6-figure EDA tools running on expensive workstations under UNIX or Windows.

Alas, it is not possible to find a group of IC designers willing to look into something that is old and lacking in glamour, [even if it is] much simpler and more efficient. The Ada I use is a small subset restricted according to an Annex in the ISO standard for safety and security, while 40 of the 46 retained keywords are also in VHDL's 96 keywords.

Now consider this. What if China picks up the Ada approach? What if the Chinese design community uses common sense due to economic necessity to avoid using costly EDA tools? Vast numbers of lower paid designers, not relying on costly EDA tools, would be able to design ICs more efficiently. That, coupled with cheap foundries, would mean that even more design jobs in the U.S would be displaced. Fortunately for American designers, China has the copy-America syndrome. China followed the U.S. in adopting Ada, and then followed the U.S. in abandoning Ada.

My message is this - Using Ada for IC design is not high tech, it's just common sense. Designers would not have to rely on costly EDA tools and would be able to design ICs more efficiently.


Dr. Sy Wong

(Editor's Note - Dr. Wong's well-known advocacy for Ada has appeared in many venues over the years.)

Industry news - Tools and IP

Agilent Technologies Inc. announced that the Shanghai Research Center for Integrated Circuit Design (ICC) has selected multiple Agilent automated test platforms, including the Agilent 93000 SOC Series and the Versatest Series for memory testing. ICC says it selected the testers to address increasingly complex and sophisticated test needs for China-based IC design houses and manufacturers in the greater Shanghai area.

Per the Agilent Press Release: "The IC industry is one of the Chinese government's key economic development projects. ICC, the first IC design industrialization center in China, supports this mission by providing design and testing resources to local semiconductor companies. The resources, including shared EDA software, multi-project wafer (MPW) projects, and sophisticated testing services, enable dozens of IC design houses in Shanghai to achieve faster time to market for their products. ICC is recognized as more than the specialized technology innovation and industrialization center for IC design houses: it is also considered the information communication and technology cooperation center for the whole IC industry in Shanghai."

Also from Agilent - The company announced that Infineon Technologies has selected the Agilent 93000 SOC test system to test the company's advanced semiconductor devices for high-speed wired communication applications.

Related to Agilent - United Monolithic Semiconductors (UMS) announced the availability of a new release of all its Design Kits that adds "significant new functionality" and targets the latest version of Agilent Technologies Advanced Design System - ADS 2003A. During the Early Access Program, UMS says it has worked in close relationship with Agilent to qualify this new release and to support its new functionality.

Artisan Components, Inc. announced that Teradiant Networks used Artisan's analog, mixed-signal, and digital IP in the development of a new high-performance configurable network-processing chipset. The TeraPacket chipset comprises a multi-service packet-processing engine and a multi-service traffic manager in versions for 10Gbps, 20Gbps, and 40Gbps performance needs. Teradiant says it used Artisan's specialty I/Os, standard cell library, high-speed memories, and high-performance 533MHz PLL in TSMC's 0.13-micron process.

Also from Artisan - In late July, the company announced the availability of its physical IP products for IBM's 0.18- and 0.13-micron CMOS foundry technologies. The company says these products are available at no charge to licensed customers under the Artisan Foundry Library Program. Additionally, the company announced that NVIDIA Corp. has adopted Artisan's design platform, including its memory products, for NVIDIA's 130- and 90-nanometer designs.

Cadence Design Systems, Inc. announced that Aspex Technology selected Cadence tools to help develop "scalable, fully software-programmable processors that deliver high performance with low power consumption." Aspex says it will "deploy" Cadence products under a two-year agreement covering every element of its design flow, from initial design to simulation and verification.

Cimmetry Systems announced that AutoVue 17.1 has been released, and that the new releases includes significant new features and a host of new format supports for tools from Mentor, Cadence, Zuken, and others.

Emulation and Verification Engineering (EVE) released ZeBu-IP, a companion version of its hardware verification system known as ZeBu (Zero Bugs). The company says the new product is configured to support IP-based design methodologies. The Press Release says that "The designer can still enjoy the speed of emulation with the accuracy of an actual hardware representation of the design and the interoperability made possible by supporting the most complete hardware and software verification environment."

Icinergy Software Co. announced that it is shipping release 4.0 of its pre-synthesis physical design exploration technology. The company says the release introduces new capabilities in three product configurations that address design flow and market-specific needs for early physical planning of SoC products and complex ASICs.

Per the Press Release: "SoC Preview is a desktop physical design exploration tool that allows ASIC vendors to conduct on-site die size estimation, power planning and part quoting during initial meetings with potential customers. Among many key functions, SoC Preview can quickly generate PDF datasheets that allow side-by-side comparison of alternative combinations of IP blocks, macros and process technologies. SoC Plan encompasses hierarchical design planning capabilities and HDL entry (Verilog/VHDL) for physical architectural-level planning, and for IP evaluation, selection and integration. SoC Plan includes advanced automatic and interactive floorplanning, IO placement and interconnect planning capabilities, and it facilitates continuous design analysis and refinement to ensure that designs meet their physical constraints. SoC Prototype adds timing-driven block placement and automatic synthesis constraint generation capabilities that guide the synthesis and gate-level handoff processes. An integral hierarchical timing budgeting algorithm extracts path information from the tool's ultra-fast virtual router to create realistic synthesis constraints that reflect delay through trial routes." The company says that users of Icinergy's SOCarchitect product will receive a no-cost upgrade to the new SoC Prototype product.

Nassda Corp. announced that TransChip Inc. has adopted Nassda's HSIM hierarchical circuit simulator and analysis tool for verifying TransChip's CMOS imager-based camera-on-a-chip designs. Per the Press Release, Tiberiu Galambos, Analog Design Manager at TransChip, said "Before HSIM, we were using a hierarchical approach with Verilog-A models, which did not permit us to run transistor-level simulations at higher levels of hierarchy that would involve many tens of thousands of devices. With HSIM, we were able to run detailed transistor-level simulations of the complete interface of the digital control and the full-custom analog imager."

Synchronicity and Royal Philips Electronics announced the successful implementation of a new semiconductor IP delivery, management, and support system built with the Synchronicity Publisher Suite. The companies say that the IP Yellow Pages constitutes a key element in Philips' semiconductor reuse infrastructure. It hosts to date 400+ IP cores from 20+ internal and external IP providers. The IP Yellow Pages is a design resource portal within Philips for exchanging IP amongst both internal and external sources.

The Press Release says, "Fine-grained access control and robust SSL encryption ensure the security of these valuable design assets, while usage tracking and audit trails guide IP investment decisions. Design blocks in the IP Yellow Pages are graded for quality and labeled with a color code, to help engineers make the best risk/reward decisions. To accelerate the selection and use of IP blocks, the system also holds associated overviews, datasheets, specifications, models, and test files. Thanks to a link to an in-house IP configuration engine, design teams can configure and download their IP through IP Yellow Pages. Whereas most IP in the system is freely accessible to all users, download access to restricted designs (e.g. priced IP from external sources) is controlled through a user request system. Through a dedicated IP Yellow Pages extranet implementation, Philips' customers involved in co-development projects can also enjoy immediate access to the IP repository."

I had a chance to speak to Paul Gibson, Vice President of European Operations for Synchronicity, on August 6th. He was en route to a meeting in Portsmouth, U.K., speaking from his car on a cell phone, while I was on a landline in Silicon Valley. You've got to love technology.

Per Gibson, "It's four and a half years since our first agreement with Philips, and now we have 1200 seats across the Philips [organization]. We've helped Philips in many ways - with multi-site collaborative design development, with integrating with other companies that Philips has merged with, and with bringing teams together from completely different companies [partnering with Philips]. And we've entered into a 6-phase process with Philips to develop an enterprise-wide reuse environment."

"Synchronicity has good traction in Europe, but we're developing a lot of new traction in the U.S., as well, with a number of large companies. Previously, those companies were using in-house tools with lots of scripts to try to make data development tools. Now they're seeing that it's far too heavy [an exercise] to write data management tools in-house or use tools that are not specific for back-end or digital design. So we're finding that we're becoming a de facto standard for data management in the development layer and in the IP reuse layer."

"We sit under the tools in a developer's design flow. They may have 70 to 100 tools in the flow, all producing data. In fact, we have one customer with over 1000 tools in their toolkit, 1019 to be exact - these are different tools and applications that their developers use from software development through to MCAD and EDA. Many designers would like to think that they'll eventually get [to a point where they can use] less tools. But bright people will always develop [new design] tools and their companies will be acquired by the big guys. Then there's the painful process of assimilation, integration of the new small tool into the flow with the larger tools."

"There will never be a company that offers all of the tools required, so we help our customers focus on the engineering data at the development layer - data that's coming in from many sources and tools. Meanwhile, it's important to be able to get data from the engineering level up to the enterprise level. We're doing that for customers and I'm heartened by the uptake from existing customers for our tools and also from other big customers which are on the rise."

Synplicity Inc. announced it has enhanced its FPGA synthesis software to provide "optimized support" for Actel's FPGAs. The company says the Synplify 7.3 software with additional support for the ProASIC Plus family is now included within Actel's Libero integrated design environment (IDE) v5.0. Synplicity says, "Customers using the latest version of the Synplify software can increase the performance of their flash-based ProASIC Plus devices by an average of 19 percent, while efficiently optimizing the device for increased area utilization. For customers requiring additional circuit performance, the Libero IDE v5.0 also features an expanded interface to Synplicity's Synplify Pro software. The latest version of the Synplify Pro software adds additional features for ProASIC Plus devices, including a re-timing feature."

United Microelectronics Corp. and Infineon Technologies AG have announced success in their 90-nanometer development program with the delivery of functionally complex circuitry using what the companies call "the industry's most advanced production technology." The companies say that this "milestone" confirms that this technology is ready to move to production later this year. The companies also announced the success of their 300-nanometer joint engineering efforts "with the achievement of high-yield pilot production for a 130-nanometer SoC IC targeted at mobile applications and incorporating sensitive analog/mixed mode circuitry. Per the Press Release, "Despite the challenges of 300mm production, these chips are currently being produced at UMC fabs at yield levels that equal or surpass those attained by similar products on mainstream 200mm wafers."

Verisity, Ltd. announced that National Semiconductor has standardized on Verisity's Specman Elite verification process automation. The companies say that National's verification teams are using Specman Elite to "speed verification of their complex SoC and IP designs, as well as ensure higher quality products. In addition, National is using several of Verisity's eVerification Components (eVCs) for standard interfaces such as AMBA AHB, USB and PCIX."

ZyDAS announced that UMC is manufacturing ZyDAS' ZD1202, an 802.11b fully compliant single-chip medium access controller (MAC) and baseband processor (BBP), on its 0.18-micron mixed-signal process technology.

Coming soon to a theater near you

ACTS 2003 - The Asia Cadence Technology Symposium will run from August 26th to September 5th in the following cities - Hsinchu (August 26), Seoul (August 29), Shanghai (September 2), and Beijing (September 5). Other sponsors include EDN Asia, EETimes Asia, HP, IBM and Sun Microsystems. Conference organizers say that more than 1,600 electronic design engineers and managers attended over the course of the event last year. This year's theme is Design to Volume and, not surprisingly, topics will include custom IC Design, logic design, system-level design, PCB design, digital design, system verification and IC packaging design. (http://acts.cadenceasia.com)

PCB East 2003 - The UP Media Group Inc. announced that Dan Shea, Senior Vice President and Group General Manager of Celestica Inc. will deliver the keynote address at the conference which runs the week of October 20 th at the Boxborough Woods Holiday Inn in Boxborough, MA. Conference organizers say that Shea will address a host of questions related to the viability/wisdom of outsourcing in today's economy.

Semiconductor Chip Start-up Seminar - Hosted by Magma Design Automation, the half-day meeting is on September 12th at the Network Meeting Center in Santa Clara's Techmart. The agenda is slated to include a VC firm's perspective on trends in funding semiconductor start-ups, a formula for measuring the ROI on EDA tools, and the inevitable customer presentations describing design success with Magma tools. Nonetheless, the day should be informative.


Aldec, Inc. announced that it has appointed Soliton Systems, KK as its exclusive distributor for all Aldec advanced mixed HDL simulation and hardware acceleration products in Japan. The companies report that Soliton Systems distributed a different supplier of HDL simulation tools for eight years. However, an internal decision was made by Soliton to transition its HDL Business Unit to focus on Aldec's mixed HDL verification and hardware acceleration products "based on the future opportunity for growth and market penetration."

Atrenta Inc. announced the closing of its Series B financing of $5.3 million. The total amount raised to date to over $17 million. The current round was led by Smart Technology Ventures and Series A investors, Venrock Associates, TL Ventures, and Finaventures.

ARM announced in July that it has purchased Adelante Technologies Belgium, a 25-person company based in Leuven which is part of Adelante Technologies Holding B.V. Adelante's A|RT technology includes a methodology for designing optimized processing blocks to accelerate high-data-throughput processing applications. The Press Release quotes Tudor Brown at ARM as saying, "ARM is committed to satisfying the bigger challenges in the industry by providing innovative, cost effective and power efficient processing solutions. The purchase of Adelante Technologies Belgium enables ARM to further our reach within our markets and strengthen ARM's position as the industry's leading IP provider."

InTime Software Inc. - Well-known EDA Executive Robert Smith, has been appointed to the position of CEO at InTime Software Inc. He was also elected to its Board of Directors. InTime Software also announced that board member Steve Ciesinski, a partner at Earlybird Ventures, has been appointed Chairman of the Board. Founder George P. Janac continues to serve as the company's CTO and a member of its Board. Smith has experience as an executive within the EDA industry that dates back to 1987. Most recently, he was Vice President of Marketing and Business Development at Magma Design Automation. He joined Magma from LogicVision, where he also served as Vice President of Marketing and Business Development. Prior to LogicVision, he spent six years at Synopsys. In addition, Smith has co-founded two companies, one specializing in silicon prototyping and the other in technical documentation. Smith holds a MSEE from Stanford University and BSEE from U.C. Davis.

Novas Software, Inc. announced that David Kelf has joined Novas as Vice President of Marketing. In this role, Kelf will oversee all product, strategic, and corporate marketing functions. Kelf, a 14-year veteran of the EDA industry, joins Novas from Synopsys, where he was Senior Director of Marketing, responsible for the strategic marketing of verification technologies and languages, including SystemVerilog. Previously, he was Vice President of Marketing for Co-Design Automation. Kelf also held a variety of marketing positions at Cadence Design Systems, and senior engineering functions at GEC Plessey and Bell Northern Research, now Northern Telecom, in Europe. Kelf holds a BS in electronic computer systems from Salford University in Manchester, U.K., and an MS in microelectronics from Brunel University in Uxbridge, U.K. He also has an MBA from Boston University.

Palmchip Corp. announced that the US Patent Office has awarded the company a patent for the company's technology facilitating the easy connection of IP blocks within an SoC design. The patent is titled Chip-core Framework for Systems-On- a-Chip.

Virage Logic Corp. announced that Dan McCranie and Robert Smith have joined the company's Board of Directors. McCranie joins as chairman and Smith joins as a Board Member. Previous Chairman Adam Kablanian remains on the Board and continues to serve as the company's President and CEO. With the new appointments, the company currently has seven directors.

McCranie has 30 years' experience in the semiconductor and communications industries. Currently, he serves as Chairman of the Board for ON Semiconductor and Xicor, and holds a Directorship with ASAT Holdings Ltd. Most recently, McCranie served as vice president of sales and marketing for Cypress Semiconductor. Previously, McCranie was Chairman, CEO, and President of SEEQ Technology. Prior to SEEQ, he had positions at Harris Corp., Advanced Micro Devices, American Microsystems, and Philips Corp.

Smith currently serves on the Boards of Cirrus Logic, Inc., PLX Technology, and Epicor. Smith started his career at Honeywell, Inc. and then moved to Memorex Corp., Control Data Corp., R.R. Donnelley & Sons Co., Maxwell Graphics, and Novellus Systems, Inc. Smith also served on the Board of Directors for Novellus until his retirement as CFO in 2002.

In the category of ...

Venn Diagram or Musical Chairs

Take set theory, your garden variety Venn diagram, and announcements over the last several weeks of new executive appointments in EDA.

In our Venn diagram, one oval represents Ken Roberts, new CEO at Pulsic Ltd. His oval includes stints at Magma, Quickturn, Cadence, Daisy, and Marconi. One oval represents Bob Smith, new President and CEO at InTime Software Inc. His oval includes stints at Magma, LogicVision, and Synopsys. So Smith's oval overlaps Robert's oval in the Magma region. The third oval represents Dave Kelf, new Vice President of Marketing at Novas Software, Inc. His oval includes stints at Synopsys, Co-Design Automation, Cadence, GEC Plessey, and Bell Northern Research. So Kelf's oval overlaps Roberts' oval in the Cadence region and overlaps Smith's oval in the Synopsys region.

There appear to be over-lapping regions in the resumes/ovals of many (dare I say all?) senior executives in EDA. Are there, per the whispered rumors, actually only 10 people in all of EDA? Should they just hold onto their existing business cards, while keeping a bottle of white-out handy for whenever it's time to insert a new corporate logo?

In fact, to the casual observer, it would appear that the "handful" of executives in EDA might just be amusing themselves - circling around the various companies in the industry like participants in a surrealistic game of corporate musical chairs. Each time the music stops, they grab the closest chair. Per this model - in this last round, Roberts grabbed the chair with "Pulsic" written on the back, Smith grabbed the "InTime" chair, and Kelf grabbed the "Novas" chair.

Here's what folks from Pulsic, InTime, and Novas had to say about all of this when I spoke to them this past week. Not surprisingly, none of them were willing to entertain the musical chairs theory. Instead, they were all quite articulate about why all of this makes sense.

Bob Smith, CEO at InTime Software

"I think this trend is good for the industry. I think people have different skill sets. In my case, I tend to gravitate towards start-up situations. I like the chaos, the unpredictability, and the ability to create something new. Alternatively, there are people who are much better at situations where things have gotten much bigger [in the corporation]."

"The thing with the EDA industry is that it's really an industry that's constantly turning over. The tech problems are constantly changing and that's why our technology is fertile ground. The technology from 5 years ago doesn't work now at 90 nanometers. That's why there's so much change in EDA."

"We're not missing new blood in EDA, because new blood comes in through entry level positions. We see lots of people that start on the technical side as developers, or application engineers, then rise through the ranks into sales or business development or marketing."

"The fact that people do move around is good for the industry. Obviously, if we moved around every 5 or 6 months, that wouldn't be good. But staying in place for 5 years or so, and then moving, keeps our industry alive."

Dave Kelf, Vice President of Marketing at Novas Software, Inc.

"I don't think there are just 10 people in EDA. I'm not sure how many there are in marketing, but on the tech side, the trendsetter is the CTO kind of guy. There are only a few of those kinds of characters and it doesn't always get announced when they've done something big. For example, when Phil Mooreby started Gateway, it wasn't big news at the time. But it grew into something huge. Those sorts of [technical talents] in EDA attract other people, who attract people like me."

"I was Employee No. 6 at Co-Design and was there until they were bought by Synopsys. Now, I'm happy to be at Novas. I was looking to be at a start-up again, but with a company further along the path and closer to pre-IPO [than Co-Design]. I feel that Novas is in a powerful position to provide technology that will change the debug market, so I'm very glad to be part of that."

"The key to innovation in EDA? Let's face it. Small companies that are still focused on individual products are the ones that provide the innovation. It takes a small-company focus to do that. Small companies have no choice but to sell one product. Therefore, their engineering guys are very driven. When you look at the companies in EDA that attract that type of person, you'll see the companies that actually innovate."

"Our changing around in the industry keeps the executives fresh and doing different things. Some executives stagnate when they get used to one environment, if they can't focus on new and different problems. Change is good - good for the industry and good for us as individuals."

Mark Williams, COO at Pulsic Ltd. (formerly CEO)

"The first thing to note is that we're only talking about top executives. When these guys move around, it's for a valid purpose. For instance, I'm a founder of Pulsic and was CEO until July 1st. We succeeded in growing this compelling technology, got traction, and quickly got to the point where the technology was in place. We had published X number of papers and then really needed to build commercial expertise into the company. That when it's time to hand the reigns over to an experience business manager."

"The innovators are typically not the executives. My moving into the role of COO is not a difficult choreography at all. I'm one of the technologists and it's a natural progression to get funding to start to ramp up on the business side of things. So the executives move around, but the innovation still comes out of the R&D [portion of the organization]."

"Back to 1998, it was quite feasible for three executives to go into a VC saying - ' I'll be President, he'll be CTO, and he'll be the Sales Guy.' - and they'd get funding. Now VCs want products that are already established. You have to have a story. And once again, you have to have a well-rounded individual to head up the company and to secure rounds of funding. Each phase [in the growth of a company] needs a different type of individual. You need to have that clear focus at the outset. You need to know when you've gotten to that next phase - when you've met your initial goals and [it's time to move one]. We're growing and hope to go all the way, to an IPO. Of course, a huge percentage of exit strategies today are M&A, but Ken Roberts (newly appointed CEO) will take us to the next level of growth and right now we're holding onto our IPO dream."

"It's a mistake to have ego involved in this process. If I had one of those large egos, we wouldn't have gotten Ken involved. But I know I speak for the other founders when I say we're delighted to have him on board."

"Of course, you would be too much of an idealist to say I'm giving up my corner office."

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-- Peggy Aycinena, EDACafe.com Contributing Editor.