Put on your walking shoes and take a tour across the show floor for an impromptu and decidedly un-scientific poll about what's going to be hot, or not, in San Francisco in July at the 43rd annual Design Automation Conference. There are 60+ responses included in this poll, and you'll know pretty quickly which were collected 'live' and which came in response to an e-mail requesting feedback.
Chuckle, if you will, at some of the market-speak here, but laugh at your own risk. Market-speak or not, there's going to be stuff going on at DAC. I think you should be there, and you probably agree. But, just in case you don't, there's even a nay-sayer - albeit Anon - in here for your reading pleasure.
And by the way, for those of you who would like to have put in your two bits - or 100 words - and didn't get the chance, we'll do this again in early July when DAC's more of a reality than it is at this time.
Warning: A number of people have told me that a) there is no buzz, or b) it's too soon because July's too far away. If that's how you feel, that's fine too.
Thanks a lot,
[Editor's Note: There were two versions of this e-mail. This one combines text from both.]
Anon - I have to ask the question: How long before the big EDA companies pull out of DAC completely? They state that it does not provide an effective return on investment and instead are putting their money into private traveling shows. Is this the whole story, or is it a continued part of their attempt to control the customer more? They have always hated allowing a prospective or actual customer leaving their booth or suite and to go and ask a competitor what they are doing to address what they just heard from another company. They want to control the customer and DAC does not allow them to set the rules.
Accellera - Accellera will hold an open membership meeting, hosting a Breakfast Panel with SystemVerilog users, and a SystemVerilog tutorial at DAC. Also, several Accellera Technical Committees will also hold informational meetings, and Birds-of-a-Feather sessions are planned. Accellera focuses on identifying new standards, development of standards and formats, and fostering the adoption of new methodologies required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. [Editor's Note: I'm going to be moderating the Accellera Breakfast Panel at 7:30 AM on July 26th. If you can drag yourself out of bed the morning after the Denali Party, I hope you'll join us.]
Adam Traidman, President at Chip Estimate (formerly Giga Scale IC) - We will make a major announcement in the run-up to DAC about progress towards our mission of aggregating IP, manufacturing, and economic data from across the supply chain to improve how designers estimate the size and cost of their chips. We believe that InCyte will become an even more significant tool this year. With 5,000 users and 30,000 chip estimations accomplished since our launch a year ago, we will move to the next level to support our goal of increasing designer productivity during the planning phase.
Alan Swahn, Vice President of Marketing & Business Development at Carbon Design Systems - At the Design Automation Conference, ESL will again be one of the hottest areas. Carbon Design Systems, a leader in virtual system prototyping solutions, will have a theater in their booth featuring presentations on advances in ESL design methodology. Topics will include system level modeling, architectural profiling, transaction-level modeling, RTL import into an ESL environment, and hardware-software co-debug.
Ashu Mausker, Vice President at Azuro - Azuro, a provider of innovative EDA tools that significantly reduce the power consumption of digital semiconductor chips, will be highlighting the latest version of our flagship product, PowerCentric at DAC 2006. PowerCentric is a revolutionary new low-power clock implementation solution that significantly reduces the dynamic power consumption of digital chips. PowerCentric brings together unique patent-pending approaches to clock-tree synthesis, clock-gate logic synthesis, and accurate average-case vectorless dynamic power analysis, to deliver a single unified clock design closure solution for power sensitive chip design teams.
Atul Sharan, President & CEO at Clear Shape Technologies - The DFM buzz will be deafening. The big EDA vendors have jumped on the bandwagon feet-first, marketing-first, products-maybe-or-maybe-not-much-later, noisily adding their DFM claims to the mix of approximately 40 'non-DFM' DFM start-ups. Attendees will have to troll through offerings to separate repackaged OPC and DRC products from true DFM tools that enable them to manage systematic manufacturing variations during design - BOTH geometry and parametric. Advice to DAC attendees? Ignore "random" noise and "systematically" look to vendors like Clear Shape that ALL major foundries have qualified, releasing hitherto untouchable FAB data/models, and being used by real designers. Ignore post-GDSII OPC offerings cleverly disguised as design tools.
Behrooz Zahiri, Senior Director of Product Marketing at Magma Design Automation - This year's DAC will prove that 65-nanometer designs are here and design teams are moving to it, to take advantage of lower die sizes and higher levels of integration. In doing so, though, they are struggling with the costly amount of manual work required to handle large designs, issues related to power consumption and DFM. Automation and the ability to address power and DFM throughout the flow is what's required to achieve profitability on 65-nanometer designs. DAC attendees can expect several technical sessions addressing these topics and companies such as Magma will exhibit products that solve such design challenges.
Brian Bailey, Chief Technologist at Poseidon Design Systems - One could claim that ESL tools have failed to address a compelling need. This could either be a problem with the tools, or that the need was not great enough. Multi-processor has started to become a significant platform for the server and desktop markets, and as this migrates into the embedded world, it will require a whole new class of tool. Those tools cannot just focus on the hardware; they have to address the software and systems aspects as well. Companies such as Poseidon Design Systems have recognized this trend and have the tools ready. Has the need grown sufficiently?
Charles Ng, Vice President of Worldwide Sales & Marketing at Kilopass Technology - Kilopass is an emerging supplier of embeddable, non-volatile memory IP implemented in a standard-logic CMOS process. The company has just announced that one of their customers, Zoran, has started to ship in volume their consumer IC products that contain Kilopass' memory IP. Kilopass will feature a number of their customer successes at DAC this year, showing how their non-volatile memory IP brings value to digital consumer ICs, mixed-signal ICs, secure ID storage, embedded boot-code, and firmware storage.
Coby Zelnik, Executive Vice President at Sagantec - The buzz at DAC should be whether we see physical implementation tools that take DFM analysis and make corrections on the mask design. DFM started in the 130-nanometer node by implementing back-end post-design techniques to address physical design, which itself is not lithography- and manufacturing-aware. Now, at 65 and 45 nanometers, DFM must be implemented in the design phase. Many vendors are developing better/faster/design-friendlier litho/yield-analysis products for the design phase. Lacking are flexible and powerful physical design manipulation tools to modify design polygons and optimize them based on such litho-simulation and yield-analysis technologies. A viable automated DFM methodology cannot be implemented without this crucial ingredient.
Craig Cochran, Vice President of Marketing at Jasper Design Automation - Structured, systematic verification is a huge trend and will be a hot topic at DAC this year. We are seeing much interest in up-front verification test planning combining end-to-end full formal with coverage-driven simulation and formal ABV, targeting the most appropriate technique to different parts of the chip. This structured combination of techniques enables users to ensure correctness where it matters most, while getting high coverage across the rest of the design and greatly improving bug hunting and elimination early in the design process. The benefits are both completeness of verification, where completeness matters most, as well as overall verification productivity.
Dale Pollek, President & CEO at ChipMD - What's hot at DAC in San Francisco? San Francisco won't be hot, it will be cold. Bring a sweater! Remember what Mark Twain said, "The coldest winter I ever spent was a summer in San Francisco." But really, what's hot at DAC will be a new way of doing things. For example, Monte Carlo and global optimization techniques just won't work any more. There are too many computational problems!
Dan Nenni, Vice President of Sales & Marketing at Predictions Software - You have to know your yield to optimize for yield! Predictions Software and Nannor Technologies have joined together to provide modern semiconductor design's first yield sign-off tool. The integration of EYES yield-analysis software and the Accuma chip-level layout optimization tool facilitates the application of full chip yield optimization techniques with calibrated process manufacturing data. In tens of minutes, process calibrated yield models supplied by the leading foundries can be applied to layout via critical area extraction and analysis. The yield trouble spots are then targeted for optimization and the resulting yield improvements are calculated.
Dian Yang, Vice President of Product Management & General Manager at Apache Design Solutions - Apache Design Solutions, a leader in dynamic power integrity and SoC noise management will be showcasing its silicon integrity platform for high-performance, low-power SoCs at DAC. Highlights include RedHawk-LP, a full-chip transient, waveform accurate, analysis and optimization solution for power-gated designs. Its ability to run full-chip power-up simulation overnight and analyze the impact of mixed-mode operation on timing is critical for 90- and 65-nanometer designs. For hands-on experience with RedHawk-LP, attend the "Hands-On-Tutorial," on Monday, July 24th. Apache will also participate in a panel discussion, "Entering the Hot Zone - Can You Handle the Heat and Be Cool?" on Tuesday, July 25th.
John Murphy, CEO at Athena Design Systems - New EDA start-up Athena Design will demonstrate its first commercial product at DAC - a new concurrent routing optimization and analysis system that accelerates the productivity of engineers, tools and computing resources so design teams can reach design closure faster with higher quality of results and lower development costs. The system is unique in its ability to automatically and incrementally “analyze-optimize-fix” on the fly using real wires. This provides the level of accuracy required for designs with 90-nanometer and finer geometries. The system works on a distributed multi-processing platform that easily integrates into existing EDA design environments.
Ellen Sentovich, Chair, 43rd Design Automation Conference - DAC will be buzzing, both on the packed exhibit floor and in the many, diverse technical sessions. It has been eight years since DAC has been to San Francisco and everyone knows this location will boost attendance and excitement, so everyone's coming. The MEGa theme, Multimedia, Entertainment, and Games, is timely, exposes cutting-edge problems, and is downright fun! With pavilion panels on topics like Inside the iPod and PSP, and Dreamworks' Innovation, and with MEGa technical sessions, keynotes, and a booth on the floor with cool demos, attendees will appreciate and be buzzing about DAC's MEGa theme this year.
Emil Girczyc, President & CEO at Summit Design - ESL and Virtual Platforms (VP) are changing companies' design methods and business models. Most of the focus has been on using VP for early software development. Virtual platforms also enable architectural exploration prior to software development. This allows designers to perform rapid architectural design and performance analysis, including “what-if” hardware/software partitioning on single- or multiple-core platforms before the hardware or software is developed. Summit's Panorama Virtual Platform Development solution provides a smooth transition into SystemC TLM models for the platform development. ESL has become a powerful marketing and pre-sales tool and a way for companies to achieve early design wins.
George Harper, Vice President of Marketing at Bluespec - DAC will be a momentous occasion for SystemC, the language that provides hardware-oriented constructs for C++ as a class library, because it will have finally come into its own. That's because there will be several developments which address shortcomings and allow SystemC to be a unified environment that can be used for modeling, verification and design. SystemC can move from being just another TLM language to a hardware accurate modeling language with full hardware implementation and architecture support.
Gerhard Angst, CEO at Concept Engineering - Concept Engineering develops and markets innovative visualization and debugging technology for commercial EDA vendors, in-house CAD tool developers, FPGA and IC designers. This year at DAC, Concept will be highlighting Nlview Widgets - a family of visualization engines (Tcl/TK, MFC, Qt, Java, Perl/Tk, wxWidgets) that can be easily integrated into EDA tools, SpiceVision PRO - a customizable debugger for SPICE based designs and GateVision PRO - a customizable debugger for Verilog, LEF/DEF and EDIF based designs. Stop by the Concept Engineering booth and see how they can bring light to your design.
Gloria Nichols, Launch Marketing - This DAC, I am most looking forward to, (1) The Denali party. I am not big on the professional 'disco' band (hint, hint Sanjay...), but I love the EDA musician performances. I went to my first Denali party last year, and it was something to remember. (2) The Dataquest event on Sunday evening, both the prognostications and all the familiar faces. As for technology buzz on the DAC floor, my bets are on DFM, ESL, and leakage power. I unabashedly admit to having clients in those areas, but it is because that is where the action is.
Jack Yao, Founder & President at Sandwork Design - Modeling and analyzing deep-submicron analog behavior have become a very important factor for yield. Fast Spice is gaining ground as full-chip, transistor-level timing simulation becomes necessary. A number of companies are developing fast Spice engines/platforms, producing a looming problem in analyzing large results data files and waveform files, sometimes with thousands of parametric sweeps. The only efficient way to bridge that gap is to use a well-integrated, best-in-class solution that provides easy access to and support for analysis of data from all three areas: simulation, hardware measurement, and system-level modeling.
Jeff Jussel, Vice President of Marketing at Celoxica - Celoxica will be demonstrating why Agility Compiler has become the tool of choice for behavioral design and synthesis for SystemC. As a single solution for FPGA design and ASIC/SoC prototyping, early TLM models can be quickly realized in working silicon yielding accurate design metrics and RTL for physical design. Celoxica tools have been used in multiple high-visibility design successes, including leading hybrid engines, "bomb-sniffing" technologies and video/image processing applications. Celoxica will also be demonstrating new hardware and software breakthroughs in accelerated computational engines bringing supercomputing power to cost-effective commercial applications.
Jen Bernier, The Hoffman Agency - The buzz at DAC? I won't be there! (I miss EDA!)
Jim Wiley, Senior Technical Director, Brion Technologies - Brion Technologies says that two design manufacturing technologies that will be hot at DAC are immersion lithography and computational lithography. Both are being used by major IC manufactures to minimize the variability in manufacturing ultra sub wavelength patterns. Computational lithography is used to apply and verify pattern proximity corrections and sub-resolution assist features to full-chip layouts - processes such as SRAF placement, model-based RET/OPC and model-based RET/OPC verification. Extremely accurate lithography process models are calibrated to simulate what will print on the wafer with nanometer accuracy. Brion will be hosting a Computational Lithography Lunch Seminar at DAC, Tuesday, July 25th.
Joe Daniels, SystemVerilog Documentation Specialist - Verification!
Julie Seymour, Senior Director of Corporate Marketing at eSilicon - eSilicon, a semiconductor company that designs and manufactures custom chips for the world's leading electronics companies, will have a significant presence at DAC, including participation by several executives in various panels: Jim Kupec, COO, will be participating in a panel, “Will the Fabless Business Model Survive?” Prasad Subramaniam, Vice President, Design Technology, will be participating in a panel, “Design Team Collaboration: Tools Challenge or Organization Responsibility.” Javier DeLaCruz, Engineering Manager, Semiconductor Packaging, will be participating in a panel, “Entering the Hot Zone.” Jayaram Bhasker, Architect, is moderating the panel, “The Xbox 360 Uncloaked: Doing What it Takes to get Chips into High-volume Consumer Electronics.”
Karen Bartelson, Director of Quality and Interoperability at Synposys - There's a lot of buzz at DAC! There's the Interoperability Breakfast on Wednesday morning. The Accellera Breakfast is on Wednesday morning, as well. There's the Accellera Technical Achievement Awards - this is the 3rd year. Of course, there's the "Chips for Dummies" course, the Workshop for Women in EDA, and the SystemVerilog Tutorial. Do you need anything more?
Kaushik Sheth, CEO of Rio Design Automation - You might be able to blame the buzz @ DAC on Rio! That's because Rio Design Automation and other EDA companies are starting to understand that designers need to factor a chip's integration with the rest of the electronic system into their design. While designers don't need to become packaging experts, this understanding is becoming crucial. This new attention of the entire system will be a highlight of this year's DAC and welcome news for companies who have missed market opportunities because they weren't “Package Aware” when they designed their chip.
Ken Karnofsky, Director of Marketing, Signal Processing and Communications at The MathWorks - ESL companies will talk about modeling hardware at higher levels of abstraction. But our customers are using model-based design to solve the real problem facing electronics companies - design flaws introduced at specification aren't detected until late in the process. They are eliminating design flaws and achieving multi-million dollar cost reductions and time-to-market advantages because model-based design ensures that the chip works the first time and eliminates error-prone hand-coding of embedded software. At DAC, The MathWorks will introduce technology that strengthens our leadership in Model-Based Design, which encompasses embedded and electronics system design and verification, and integrates with downstream tools for implementation.
Kevin Steptoe, Vice President of Marketing & Business Development at Pulsic - Analog, mixed-signal, and custom digital will take center stage at DAC this year as companies have concluded that high-volume IC design is a highly specialized arena where yield, area, and performance are commercial priorities. In high-volume markets, tuning nanometer, full-custom designs to maximize yield and profit has been an iterative and largely manual design effort. As the circuitry in these designs grows - for example NAND-Flash control logic is growing rapidly - physical design automation is becoming the only way to design these chips. Expect to see a new physical design automation tools and methodologies at DAC.
Lauro Rizzatti, Vice President of Worldwide Marketing & General Manager of EVE-USA - Verification will continue to be a topic of discussion during DAC this year, especially the growing use of next-generation hardware assisted verification platforms for simultaneous hardware and embedded software verification. These fast, reliable machines shorten time to tapeout, improve product quality, eliminate re-spins, and accelerate software development ahead of silicon. These systems are replacing existing emulators bogged down by slow speed and high costs. Older generations of emulators have been relegated to hardware debugging applications and can't be used for the most pressing needs of a design team: hardware/software integration and embedded software validation. Design processes are combined in a seamless development environment.
Linda Prowse Fosler, Vice President of Marketing at VaST Systems Technology - VaST is sponsoring a panel on ESL design and verification at DAC, giving a tutorial on using virtual system prototyping to design and optimize SoC architecture and parallelize hardware/software development, and unveiling the sixth generation of its embedded software development tool. CEO Alain Labat says, "ESL is coming of age due to growing market need and the pressures for on-time product delivery. Silicon embedded systems have huge software content and market pressures that no longer tolerate serial software development. Real embedded system design solutions that enable high-speed, cycle-accurate concurrent hardware/software design are a critical part of ESL tools and methodologies and are available now."
Max Lloyd, CEO at ViASIC - There'll be a lot going on at the ViASIC booth at DAC. One of our customers, Triad Semiconductor, will be presenting their via-configurable mixed signal array products, which use ViASIC's ViaMask technology. ViASIC will also be unveiling a new product, as well as releasing a new process-node of the ViaMask standard-metal one-mask library for 90-nanometer technologies. Standard-metal libraries can be used to build structured ASICs or as a fabric for developing rapidly configurable sections of an SOC.
Michel Ligthart, COO at Verific - There's nothing hot at DAC, but that's not important, because DAC is the place for me to see my customers, to interact with academia and other vendors. It's all there and more than enough of a value proposition for the conference. It's not like a car show, where you have to have new products every year!
Mike Gianfagna, President & CEO at Aprio - DFM is hot...or is it? How can anyone wade through all the hype and figure out what's real? Aprio will set the record straight at DAC. Through a series of announcements in early July, we will unveil our roadmap for a comprehensive design-for-manufacturability solution, spanning both manufacturing and design applications. Aprio's approach takes aim at the poor communication that exists today between IC design and manufacturing teams. Through partnerships with key suppliers in the design-to-manufacturing chain, Aprio plans to improve chip predictability, performance and yield with minimal impact to current design and manufacturing workflows. That's what DFM should be.
Naeem Zafar, President & CEO at Pyxis Technology - There will be a lot of talk about DFM at DAC this year. IC designers will hear about new tools that identify manufacturing and yield problems. Multiple vendors will offer lithography simulation, parametric analysis, and yield analysis that can be incorporated into existing IC design flows. However, existing IC design tools are unable to take full advantage of these model-based capabilities. They do not have the ability to avoid DFM/DFY issues during implementation. New startup, Pyxis Technology, brings IC designers a correct-for-manufacturing environment that optimizes designs for the manufacturing process and improves design yield while achieving design closure.
Nitin Deo, Vice President of Marketing & Business Development at Ponte Solutions - Ponte Solutions will showcase a yield sensitivity analysis system for nanometer designs. Yield Analyzer is built on the foundation of unified models for mission-critical yield issues for any designer of cell libraries, memories, IP, block-level or chip-level designs. For these designs, design rule checking is not sufficient anymore. In order to identify the trade-offs, the designers need a model-based analysis system with actual fab-correlated models. Ponte's Yield Analyzer, delivers accurate analysis for designers to focus on the right optimization techniques.
Open SystemC Initiative - OSCI is hosting a SystemC Technology Symposium and a North American SystemC Users Group Meeting on Monday, July 24th. You'll hear from industry experts speaking on recent SystemC advancements and using SystemC for doing real world system-level design. Status updates on the technology roadmap, IEEE 1666, and TLM will also be presented. The event is sponsored by Cadence, Celoxica, CoWare, Doulos, ESLX, Forte, Mentor Graphics, and Synopsys.
Paul Rowbottom, Senior Marketing Manager at Advantest Technology Solutions - Advantest Technology Solutions will demonstrate its new CertiMAX product. CertiMAX enables "real world" event-based semiconductor validation using a PXI-based environment without imposing any of the traditional limitations of cycle-based test. It revolutionizes the validation environment by allowing the functional verification, debug, and characterization of first silicon without deviating from the design environment. Chip designers can literally take an industry- standard VCD file from a simulation tool and use it as is, on silicon. By allowing the design data to be used directly without requiring vector, timing, or format translation, CertiMAX greatly simplifies the validation process DRAMATICALLY speeding time to market.
Randy Smith, RLS Consulting - What's hot at DAC will be DFM, especially the D part. Most of the talk has been on the manufacturing side, but there should be a balance. That's going to be a big part of DAC, plus more and more discussion about open source and Open Access. Users will have many more choices in how to construct their design flows.
Rich Goldman, Vice President of Strategic Market Development at Synopsys - At DAC, the system-level issues will be key, plus developments in IP. We have a panel session on where Dreamworks-based animators will show how they translate their work into a movie. That's going to be very cool!
Robert Hum, VP & General Manager Design Verification & Test Division at Mentor Grapics - The buzz at DAC? It's very simple. The vendor floor will continue to consolidate and the show is going to turn back into a technical paper show. DAC will go back to its roots as a show for technology.
Robert Pierce, Senior Director of Flash Products at Denali Software - System developers attending DAC will have lots to celebrate as new embedded software products emerge to help deploy high-quality flash memory systems for a wide variety of applications, from handsets to network routers running multi-threaded applications. Jim Handy, flash market analyst at Semico Research, says that one product in particular, Spectra from Denali, appears unique in its ability to support both NAND and NOR-based systems: “Such an approach frees system developers to choose from a wider range of options, and to adapt their designs to changes in market conditions or advantages provided by one technology or the other.”
Sandipan Bhanot, President & CEO at Knowlent - The buzz at DAC should be: Will any analog vendors step up and provide the tools to make analog signoff a reality? Analog design has always been a black-magic art. SoC tapeout is being impeded by the analog components - the digital portion of the SoC is ready to go, but waits for the analog/mixed-signal portion to be verified. We need to toss the old analog black magic out, and get analog to catch up with digital design. We need an analog signoff design flow and a formal methodology to go from design entry to post layout verification. It's high time for analog to catch up with digital design.
Sashi Obilisetty, President & CEO at VeriEZ Solutions - It is never too early to build up momentum for DAC - I don't for a second believe that some EDA vendors think DAC is too far away when we all know DAC 2006 planning began on the last day of DAC 2005! This year, I think we will start seeing some real interest in SystemVerilog-based verification flows - the verification news groups are buzzing with early adopters already. A substantial amount of interest will revolve around verification libraries, such as RVM from Synopsys and AVM from Mentor. Verification, in general, is always high on the users' list, but this year there will be a surge of interest from users seeking ready-to-use tools that support functional coverage, SystemVerilog testbench, and verification reuse.
Simon Davidmann, President & CEO at Imperas - One of the more exciting developments for the EDA community and one that will cause a “buzz” at DAC is the emergence of Multi Processor System-on-Chip (MPSoC) design. The electronics industry is entering an era of discontinuity, which offers a remarkable opportunity for those willing to seize it. Designers are finding that the average number of processors per MPSoC is growing and existing tools don't work for the new class of multi-processor chips. Developing and programming MPSoCs will require a unified systems design automation approach, where hardware and software technologies and design processes are combined in a seamless development environment.
Simon Young, Senior Director of Marketing at Xoomsys - Why compromise the integrity of your final circuit simulation verification? Why risk having your chip fail because of dynamic voltage drop, or functional or timing noise? These unanticipated interactions inject uncertainty and error into verification, causing functional and parametric failures. To prevent these latent design issues in silicon, your post-layout verification must consider, with high accuracy, the impact of dynamic coupling. At DAC, renowned EDA researcher Dr. Resve Saleh will present at the Xoomsys booth, the growing crisis of reduced design success resulting from the causes and impact of dynamic coupling. Xoomsys' solution is based on its unique distributed processing circuit simulation solution.
SPIRIT Consortium - SPIRIT is having an event at DAC on Monday, July 24th where the member companies will be talking about progress made, and new plans for the future. It will be a very interesting event and the entire EDA community is invited to attend.
Steve Ohr, Gartner/Dataquest - If Christian Heidarson is right, major markets in analog design can solve the problems, although Christian and I may disagree about how easy that may be. The trouble is that everybody uses Spice on full-chip verifications. After that it has to be hand crafted. People are going to be talking about that at DAC.
Steve Schulz, President & CEO at Si2 - This is the year of Open Access adoption! We'll be seeing additional vendor products announced around the standard at DAC. I'm hearing, also that it's more and more about collaboration, and that not just around Si2, but an overall industry trend. At 65 and 45 nanometers, the problems are forcing a more collaborative effort, particularly in developing the design tools!
Sunil Mudinuri, Marketing Manager at Zenasis Technologies - Power will be a big DAC topic, and at 65 nanometers, leakage power is the king of power problems. Designers will take advantage of DAC to find out which vendors have attractive leakage power solutions. The reality is that leakage power must be optimized in the context of the design's timing and area requirements. Furthermore, though 'timing' as an issue was identified a long time ago, it is still a major hurdle for design teams, and some of the emerging solutions are worthy of 'buzz'. Zenasis will be showcasing its recently announced ZenTime optimization products for timing, power and area.
Tets Maniwa, GabeOnEDA & EDA Confidential - Features of analog design are going to become much more important to the overall design. In my personal opinion, we need to back off on SoC design and move to multiple chipsets that are optimized for the process. Assembling designs on one chip is a bad idea - that's got to start changing.
Tom Grebinski, President & CEO at OASIS Tooling - OASIS Tooling has spent the last two years working with the leading developers and users of OASIS, the new data format replacing GDSII. Exhibiting at DAC this year for the first time, the company will demonstrate the broader capabilities of OASIS encountered at this leading edge worldwide implementation including advanced OASIS infrastructure, applications, verification, functionality and OASIS acceleration hardware.
Tom Ferry, Vice President of Marketing at Berkeley Design Automation - Berkeley Design Automation provides circuit analysis tools that improve the design and verification of analog and RF ICs. Our Precision Circuit Analysis (PCA) technology closes the analysis gap between what designers can accurately simulate using traditional tools and what is measured in silicon, by allowing designers to fully characterize designs before tapeout. PLL Noise Analyzer, the company's first product, is based on PCA technology and is the only tool that accurately characterizes PLL noise at the transistor level. Our products have been adopted by more than ten of the world's leading semiconductor companies and used on designs manufactured from 0.5 micron to 65 nanometers.
Tom Quan, Vice President of Marketing at Applied Wave Research (AWR) - The general buzz continues around the path to maturity and rate of adoption of sub-100 micron DFM technologies and flow. Also hot - analog/RF tools and IP targeting wireless market. For AWR, DAC will mark the beginning of a new direction and focus, "RF design for the masses," by getting our open RF design platform deployed and adopted for designing next generation RF devices. The concept-to-implementation platform, already adopted by thousands of microwave engineers, and now with almost 100 man-years of additional development, is the industry's first and only high-frequency design platform fully integrated with 5 EM simulators, 4 circuit simulators, and 3 physical verification toolsets.
Tom Sandoval, CEO at Calypto Design Systems - Calypto Design Systems moves ESL design from theory to reality with the SLEC v2.0 sequential equivalence checker, the final element completing a true system-level design methodology. Calypto has introduced many product enhancements to SLEC, including a 100x capacity increase, while attracting several top 10 semiconductor companies to its customer base. Calypto will take part in the DAC special session, "Bridging the System to RTL Verification GAP," plus a luncheon panel, "Lessons from the trenches/real-world ESL project experiences - are the advantages worth the cost and effort?"
Tor Ekenberg, CEO at Manhattan Routing - Manhattan Routing will be showing their Physical Window/Optimization Cockpit (PW/OC) solution at DAC 2006. Based on the semi-automatic analysis and targeted optimization features of the tool suite, MRI has developed an automatic solution for closing timing in multi-mode/multi-corner designs. While this automatic solution cannot replace the manual analysis and optimization effort that PW/OC was designed to address, running the automatic optimization step prior to any manual work allows many more timing violations to be addressed automatically. This automated solution is available now and is shipping as part of the OC package.
Victor Berman, Group Director of Language Standards at Cadence Design Systems - There are two main areas of interest: (1) Integrated approaches to power management for 90 nanometers and smaller geometries: It is no secret that the biggest problem that system integrators are facing is the challenge of low power for mobile and consumer products. The most interesting approaches here will be integrated design and verification systems that span the space from architecture through silicon implementation. (2) Maturation of SystemVerilog and SystemC verification infrastructure: The advanced design and verification gurus have accepted the fact of multi-language environments for executing on complex SoC designs. Look for open standard approaches to providing the verification.
VSIA, FSA and Chipestimate.com are sponsoring an event on Monday, July 24th: “How Many Engineers Does It Take? The Real Issues in IP Integration.” IP integration and verification is only getting more complex, expensive, and risky. IP suppliers, integrators, EDA vendors, and foundries must work together in a streamlined fashion to ensure IP success. But are they? Varying degrees of IP quality coupled with a host of business and technical issues makes IP integration the key challenge in modern SoCs. Don't be left holding the cards with your next chip design. This panel will expose the interrelated and often opposing technical and business issues surrounding IP integration and explore how this fragmented industry can work together. Panelists will include Chip Estimates' Adam Traidman, Open Silicon's Naveed Sherwani, Virage Logic's Jim Ensell, TSMC's Kurt Wolf, and IBM's Raminderpal Singh.
Wayne Wolf, Professor of Electrical Engineering at Princeton & Publicity Chair for CEDA - The IEEE Council for Electronic Design Automation [CEDA] has the opportunity to create the “buzz” at DAC with the continuation of its Distinguished Speaker Series Monday, July 24th. A beer and refreshments reception will be followed by a talk from the yet-to-be-announced winner of this year's IEEE Transactions on CAD Best Paper Award. The author will give an in-depth presentation of their work, offering far more detail than the published paper. This event is open to all and offers the promise of meeting new people, while hearing an interesting talk on a cutting-edge EDA topic.
Editor's Note - Thanks to everyone involved in pulling together this first round of commentary on Buzz@DAC.2006. I'm grateful for your help. And, thanks to Ed Lee at Lee PR for the conversation that led to the idea of doing the survey in the first place.
(Photo of De Young museum from the museum website, http://www.thinker.org.)
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.