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April 30, 2007
Device Native Verification of FPGAs - GateRocket
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


According to Gartner, worldwide ASIC design starts have declined to fewer than 4000 in 2005. At the same time, FPGA design starts are currently running at over 90,000 a year and rising.

On April 23 GateRocket Inc. announced availability its Device Native verification product that gives FPGA designers the power to validate designs with one to two orders of magnitude faster simulation, and realize actual device behavior early in the design process. RocketDrive is a hardware and software solution that adds significant value to existing design verification environments without a change in design flow or verification methodology.

Prior to the announcement I had an opportunity to interview Dave Orecchio, company president and CEO

GateRocket is all about accelerating product design. We have an approach we describe as Device Native verification. We focus on helping people who are designing the large FPGS devices. Our view is that we help those engineers who are designing these large FPGAs for all the cool electronic products that people interact with on a daily basis. It is amazing as I dove into it to see all the applications that are starting to use FPGAs. I think that as time goes by more and more will. Certainly the people who are designing these chips are facing a crisis in their ability to verify their designs.

Would you provide us with a brief biography?
I’ve been in the semiconductor space, the EDA space for the lion’s share of my career. With the exception of 2 years when I did a stint for Parametric Technology. I was SVP of Product Management for the Windchill product line. I decided that I wanted to return to EDA. Basically I started working for LTX Corporation, a semiconductor testing company, and then moved into EDA during the very early years of Viewlogic Systems. I worked for the company pre and post IPO through the growth years with its many acquisitions and through being acquired by Synopsys. I worked for Synopsys. We then spun out a portion of the technology and renamed it Innoveda. We ultimately sold that product to Mentor Graphics. Most recently I led Marketing at DAFCA which is in the SoC validation and debug space. I have a lot of experience in the EDA space and really enjoyed working in this area. I think there is a lot of opportunity. I always look for ways in which I can find a solution that can be significantly impactful to the market. The thing that excited me about GateRocket is that there is a significant, large and growing marketplace for large FPGA design that matter in the industry. And there is a problem with verification of these designs.

You have worked at both small and large firms. Now you are back at a small startup. Do you have a preference for small firms? What is the difference between working for a Synopsys and a GateRocket?
Good question. When I joined LTX they were a startup. I helped them until they became a bigger company. Then I decided to join another startup called Viewlogic Systems. Each of these tenures was long. Actually at LTX I spent 9 years. I like starting in a company that is small and helping them scale and grow into a sizeable business. That would be the best characterization of myself. In the case of Viewlogic they were a startup. When I joined the company Alain Hanover who is now the Chairman of GateRocket was leading Viewlogic. They sold the company to Synopsys. I stuck with the part that was a wholly owned subsidiary. The plan was always to spin it out again. We spun Viewlogic back out and named it Innoveda. It was basically the FPGA and system tools. This was in effect another startup because we had to get financing to buy the product that Synopsys was not interested in. We founded that company and it grew to a point where it was desirable for Mentor to acquire it. If you count those three firms, they were all small companies that grew to become larger companies. DAFCA was again that type of experience. DFACA was financed by VC firms. When I joined them they had a PowerPoint deck, an idea, VC funding and an opportunity to make something that is great. I joined them and helped bring that product to market. In the case of PTC that was simply an interest in a market segment. I was interested in the product lifecycle management area that touched a different perspective of product development.

I would have to say that I am more of an entrepreneur who likes working for small companies and helping them grow to become larger successful companies.

Chris Schalick now CTO was the founder and your predecessor as CEO.
Chris Schalick, an MIT alum, worked for several years at PacketEngineering and Tenor Networks. He built chips for communication companies. With this experience he moved to Teradyne who had moved the majority of their chip design from ASIC to FPGA and very large one at that. As he was doing that he applied the same methodology as an ASCI designer would do in building products. As he was going through the debug phase on the chip on the board, he found that designs that worked in simulation with test benches would not work in the system. He realized that the tools that are needed to effectively tapeout for an FPGS on a board do not exist. He had a new vision of the way to solve this problem and that is what inspired him to found GateRocket.

A lot of startups do not do it this way. Most startups get an idea and go to the VCs to get financing for it. He did it the other way round. He bootstrapped the business on his own nickel. He spent 18 months building a product and establishing customers. And then he realized funding to scale the business. He did a fantastic job. He had help. You may be familiar with the IT Mentoring Group. MIT has a great program where they advise young entrepreneurs in the early stages of developing the business and developing the company. They were instrumental in helping to guide Chris during the early months through the first year of life for the company.

You mentioned Alain Hanover.
Alain Hanover, one of the founders of Viewlogic, is the Chairman of the Board. One of the things that excited him about GateRocket was the similarity of the value proposition to that of Chronologic’s VCS product. If you think back to the early days of Viewlogic we acquired Chronologic which was a Verilog simulator. Frankly the only value proposition it delivered was that it was 10x performance improvement for verification. We had a rare experience for that product. The sale people were literally sitting by the fax machine as orders were coming in. It was one of those products that sold itself. In the early days of Verilog simulators you still had issues but customers were willing to go through all kinds of machinations to utilize it in order to get the 10X in verification performance. This was one of the main values of GateRocket that excited Alain to get involved as well as the maturity of the technology at the time of financing.

We also have an advisory board. The most recognizable name is Mike D’Amour, the founder of QuickTurn. He was excited because he saw that when you talk about the classification of products that are a combination of hardware and software for the purpose of verification, this technology has all the value without the pain that traditional users faced using this kind of product.

Where did the company get its financing?
The company was founded in 204. We had the first prototype several months later and filed a patent with 53 claims. In September 2006 we received financing ($1.25M) in a round led by Common Angles. That’s when I officially joined the company although I had been working with them for several months. We are talking about an April launch of the product.

$1.25 million does not sound like a lot of money. Are you thinking about raising additional funds?
Chris created this opportunity when he developed the product on its own and brought it very close to being realizable to the market. There was some polish that needed to be done on the product. We are now ready for full commercial release of RocketDrive. Our goal now is to grow the business with our early financing and over the next few months we will be evaluating what we do. If and when we were to approach additional financing, it would be with a goal of aggressively ramping up the revenue. At this time we have not made any decision with respect to any additional financing.

How big a company is GateRocket?
We have 6 fulltime employees and a host of consultants. I have established a network of value added resellers to sell this product across the nation. This year we are focusing mainly in North America. Our plans show us expanding internationally in ’08 from a sales point of view.

What is the challenge that GateRocket faces?
Part of the challenge in being an EDA company is that the majority of the attention is given to the ASIC design flow. Unfortunately not many people focus on the FPGA. The trends are staggering. There are 15 times the design starts for FPGAs than there are for ASICs. ASIC starts are in the range of 3,000 starts annually. According to Gartner they are expected to stay in that range through 2010 while FPGA starts are expected to grow in that same period. We as a company focus on large FPGAs. I would define large as anything greater than 40,000 logical elements which frankly is relatively small but it is large enough that people with designs that size are experiencing these problems. Simulation is just too slow. People building systems with FPGAs are now running into the same problems that ASIC designers are. FPGAs are now the modern ASICS. People who use chips to consolidate logic or design new systems are implementing in FPGAs first as a methodology of getting to market faster. Simulation is too slow and by and large can be inaccurate. When we simulate a design, we simulate a model. The simulation results are only as good as the models are. In my experience when I talk with our early customers about their experiences, every single customer to a man says that they are utilizing some third party IP and the behavior of that IP under simulation is different from the IP on the actual FPGA. Companies are frustrated by that problem. When I say inaccurate, I am not saying that simulation does not work. That is not true at all. It works bit it is only as good as the models you give it. If what they are designing does not behave on the physical chip the same way as it does in simulation then as far as the designer is concerned it is inaccurate. If the simulation for a single chip is slow, then designs with multiple chips are far too complex for simulators to handle. Nowadays systems have multiple FPGAS and companies want to be able to validate these designs.

I can’t mention the name of the company but I had a discussion with a prospect who has a board and they are in the process of respinning one of the ASICs on that board that has been around for years. The plan is to respin the ASIC into an FPGA. The guy said that the goal for doing that was to reduce the power dissipation of the overall board. It turns out that with some of the new FPGA technology, FPGA vendors have the opportunity to take advantage of deep submicron technology and deliver a standard part. As new FPGAs come out they are consuming less power. If I compare an old ASIC to a new FPGA they have the ability to respin an old ASIC with a new FPGA and eliminate the cost of the NRE. I though that was an interesting story. Obviously, if you compare gate for gate, a modern 65 nm ASIC versus a 65 nm FPGA, the ASIC will consume less power. But a lot of companies are factoring in multiple dynamics in their decisions. They factor in the cost of NRE, multiple spins and the time it takes to get there.

If I look at an ASIC design, a designer gets to the point where he has a simulation model of the design and he has a test bench. He is able to test all the paths to the point where he can declare that he has a known good design and now needs to iterate through synthesis and place and route until he gets a known good chip. The ASIC designer starts with a known good design and iterates to get a known good chip. For the FPGA designer the whole process stands on its head because eh FPGA vendors like Xlinix and Altera give the designer a known good chip and he or she has to iterate until they get a known good design on the FPGA. The problem is flipped. The fact that we have a programmable chip gives us a lot of opportunity to create products.

What is the product that you are launching?
We are introducing RocketDrive. It is a solution for faster, more accurate FPGA verification. We deliver depending upon design size 10 to 100 times simulation acceleration with the same behavior as the target FPGA family. At launch we are supporting Xlinix and Altera. It is a scaleable system. We can provide verification for up to 8 simultaneous RocketDrives. This is not a solution that eliminates the simulator. It complements and supplements the simulation environment. There is no methodology change. It is easy to integrate into the existing environment. There are only minor changes in the test benches. We have a philosophy about our product that it is very easy to use, something that fits into existing methodology and adds value without forcing anyone to change methodology or approach. The other thing we have done is gotten very creative with the form factor of the product. It looks like it would fit in a standard ¼” PC form factor and it does. We install this RocketDrive into any Linux PC that the customer has. It interfaces through a PCI card. Our software is economically priced. We want to be very aggressive with respect to the market and help people leverage these as quickly as possible.

One thing I will tell you to eliminate possible confusion is that even though we call it RocketDrive there is no hard disc in it. Inside the RocketDrive we put the largest FPGA in the FPGA family of Altera or Xilinx. The electronics provides accessibility to to integrate that FPGA with the customer’s simulator. In essence what we are doing is connecting or bringing the FPGA device into the loop of simulation. That’s why we call it Device Native verification. You can think about it that any part of the design that the customers place onto the FPGA in the RocketDrive compared to software simulation. The premise is that the customer can move what he wants from his simulator or the RocketDrive to get acceleration for that part. He sees the actual behavior of how the device will work when it winds up in the system. He is seeing the behavior of the design not in simulation but on the chip. Obviously if you have a system with multiple FPGAs on it, he can implement a system with multiple RocketDrives that are connected to a simulator. Think of the simulation test bench environment that the customer has as an infinitely flexible virtual prototype environment. The simulation test bench is like a virtual printed circuit board that provides the connection between one or more RocketDrives and the test that the customers wants to run against the design. In essence that’s what the RocketDrive is all about.

Any design nowadays has multiple elements of third party IP, logic, a processor and other components. Customers are generally using one of the top simulators; Cadence or Synopsys. We integrate the RocketDrive into the simulator and we utilize the largest members in the Xilinx or Altera family. The customer can decide which portions of the design to place in the RocketDrive. If I am doing a new design and someone has given me some IP that I have never seen before, I can move this IP and its testbench alone into the RocketDrive and see if it behaves the same way as the simulation model and what kind of behavior I am getting from the IP on the RocketDrive. Or I can put the entire design in the RocketDrive and see how it works. Before I get into the lab with the end product chip on a board, I really do not have the tools to see what is going on. I can actually validate how the design is going to work on the chip.

Another use model that we believe people will want to utilize is for doing a new design that is a derivative of an old design. Let’s say three quarters of the design is from an old design. In that case I would put the three quarters onto a RocketDrive and I keep the part that I am iterating within the simulator. I am always comparing the piece I am changing to the part that is running and behaving as it would on chip. I am getting acceleration for that part of the design so my productivity is better. I am comparing against everything else but I got the productivity of iteration of the actual simulator.

If the design involves multiple FPGAs, would not one need to partition the design say with Simplify from Synplicity? How would this impact the use RocketDrive?
Any RTL that can fit into a single FPGA can be put onto a RocketDrive. We do not do any partitioning. We leave that to the designer or tools that they use. For example if someone were using Simplify as a way to take a large piece of RTL and break it into pieces, then we are a partner with Synplicity and support the use of Simplify to synthesize into the FPGA on the RocketDrive.

If I assume that the FPGA on my printed circuit board is as close to reality as my end product as possible, I would call that 0 level of abstraction. Once I have my design on my FPGA on a printed circuit board and all my circuits connected to it, it is as close as possible Software simulation of that product is one level of abstraction away from the actual product because you are simulating models. Traditional technology that exists today, namely hardware emulators, tries to be technology independent. They are targeted at very large ASCI solution. The way they work is to take a design, break it down into its fundamental elements (AND and OR gates) and then partition the design into proprietary hardware. There are a dozen companies that support this kind of methodology. The challenges they run into with companies trying to use that approach for FPGAs is that FPGAs have different amounts of intellectual property. The models are either specific to the FPGAs technology itself or third party IP that is provided for that FPGA. In order for the hardware emulator to work they need special models that fit and support that particular emulation environment.

What does it means to be device native? What we do we take the software simulation, integrate the actual chip with the simulator to bring the physical device into the loop with simulation to give the use all the power and flexibility of their verification environment augmented and enhanced with the actual chip.

We are actually giving zero level of abstraction since they have the actual chip in the loop.

One of the other stories to tell here is that we ask the customer “Do you have the capability to program your design into an FPGA? Do you see any technical issues with that?” First of all they take ownership for doing that because that’s in their end product. Secondly, it is a solved problem, getting a design into an FPGA. They say yes. Well, if you can do that then you can leverage a RocketDrive. There are no issues relating to FPGA IP. If they have the right to build that IP onto that FPGA, they can use it on a RocketDrive. There is no translation, no mapping, and no partitioning. It just fits. It just goes. Our promise to our customers is that any design that is FPGA ready can be placed into a RocketDrive in a morning or less.

How is the product packaged?
The first configuration is the RocketDrive itself. We sell that as a unit to be installed in the customer’s system. I have to say that all of the companies that we have been engaging with early on have asked to have the RocketDrive installed in one of their systems. I do not think anyone has asked us to ship one but we can offer that. The second is a single user system intended to fit on top of engineer’s desk and augment his environment. Then there is a server based system that allows us to program and design a chip on multiple RocketDrives, up to 8. So you can have a system with up to 8 FPGAs verified together with a test bench and validate that system. At our launch we are supporting Altera Stratix II and Xilinx Vertex 4, the largest FPGAs in those two families. Sometime in the summer we will also implement on Stratix III and Vertex 5 devices. We will wait for our customers to tell use which is the priority for them before committing to which one we do.

As far as software is concerned, it comes packaged with the RocketDrive itself. RocketDrive software is software intended to be used in a regression environment. It allows you to take whatever design you want into a RocketDrive.
RocketVision is a tool that allows you to select which portions of the design to fit into a RocketDrive. It is not really partitioning. It says which parts go into the RocketDrive while the rest stays in the simulator. It is a variation on the theme of how you select what is and is not on the RocketDrive. That’s an optional feature.

Is the server to accommodate one large design on multiple RocketDrives or to allow multiple designers to share the device or both?
The intent of the server is not to have multiple users. It is intended to have multiple prototype solution for designers with multiple FPGAs running at the same time. In the case of RocketDrive, since it is a physical piece of hardware, only one design can be pushed through the drive at a time. Although our software is intended to be inserted into a standard regression environment it is command line driven so that you can script it. If I am running a server farm with regression runs for my design, this solution can fit seamlessly in conjunction with that environment.

What is the pricing for the hardware and software?
The PCs are priced at around $2,500. It doesn’t matter whether it is a single or multiple system. The drives themselves start at $25,000 each. In a multidrive system you would buy whatever flavor RocketDrive you need and as many as you needed.

One thing I might mention that the RocketDrive is hot swappable from the front case so that if in morning you are working on Altera Stratix design and in the afternoon you want to work on Xilinx Vertex 4, you can take one RocketDrive out and put the other one in. I imagine that in some cases companies would buy server system for the purpose of validating the overall product but the RocketDrive would be on individuals’ desktop as they design their piece of the system. It is when they bring it altogether that they would place the RocketDrives in the server solutions. The customer does not have to buy as many RocketDrives to fully populate all the systems. They can do this very economically.

The goal of RocketDrive is to be easy to use. Our promise is that any FPGA ready design can be ported to the RocketDrive in a morning. The hardware solution, if you talk to users, typically takes weeks because of design spins. In many cases they are struggling because the designs once they are in do not behave the way they did under simulation.

We help them expose system bugs early in the design process. They tend to eliminate a whole class of bugs that would occur when you went and installed the FPGA on the board in the system. The customer can be assured that the functional issues are resolved prior to getting to that stage. It complements existing methodologies and tools. We are partners with Cadence, Mentor and Synopsys in simulation because they add value with their simulators. In fact you can not use the RocketDrive without a simulator. We work in conjunction with the simulator and add value to it. We also integrate with the design tools the engineers are using for FPGA be it Kronus or Synplicity.

It is an economical form factor. An analogy I will draw from the ASIC flow where the ASIC design starts with a known good design and iterates to a known good chip to the tools the ASIC designer uses in the process. He or she uses formal verification to compare the input of synthesis to the output of synthesis. He or she uses LDS to compare the input of layout to the output of layout. They want to make sure that any of the translations of the designs do not get corrupted by the tools they use for synthesis or layout. You can think of RocketDrive like an effective and easy to use formal verification and LDS for FPGAs because you are able to see and run simulations against the design that is actually running in the chip. So you have been through the synthesis and place and route but you have access to all the tests you created in RTL to validate that the stuff is working the way you expected. It’s another value point that isn’t obvious unless you really think about it.

It takes a little bit of time to think about it and get your head around the fact that you now have an FPGA and you can use it to test itself more or less. We are delivering it in a way that is seamless to the designer. If I am a designer and I have a design, a DUT, my tests and my instance name of my DUT is FOO, then I just change the instance name to point to the RocketDrive and I am up and running. Very, very simple. You get the real chip behavior in a simple and efficient form factor.

To the best of your knowledge there is no direct competition. Existing software simulator are slower and existing FPGA prototype environments take weeks or months to bring up versus a morning with RocketDrive.
Exactly! The key difference with an evaluation board you might buy with an FPGA on it is that the pins on that FPGA on that board are predefined. The circuitry you are connecting to on that board is also predefined. It is a project to get your design to work on evaluation board. There has to be an engineering project to get there. Secondly, once you get there, all the tools that are available there do not easily help you to translate the issues you find. They are at the gate level not the RTL level. You can not translate how this works in a simulation environment. We basically give the user the ability to have the chip in the simulator. Frankly the test bench of a simulator is a very productive environment for the verification of a new design. And it is flexible. I can change connectivity to the chip. I can change the way the pins are specified. I can change virtually anything. I can move the pins around. I can change the way clocking is applied. Anything you can do and anything you can program on an FPGA you can do on a RocketDrive. There is no restriction for the user with regard to that.

Although our focus is FPGA design we have no qualms to provide RocketDrive to someone who just wants to accelerate their RTL. RTL is technology independent. There is no translation needed. We are happy to talk with those types of customers. I was approached by a chip company. I went into to present to the VBP of Engineering. I gave him a 15 minute courtesy presentation. He went out and brought in 2 engineers that he got out of a meeting. They asked me a few technical questions. Then in walked the COO of the company, the person responsible for the design and manufacturing of the chip. I did the presentation again. He said the concept was so simple that even he, who had been out of the trenches for years, could understand it. It is a simple concept but making it easy to use is an art and in developing RocketDrive we have done that,

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  • North American Semiconductor Equipment Industry Posts March 2007 Book-To-Bill Ratio Of 1.00
  • AMD Reports First Quarter Results  
  • SiRF Technology Holdings Inc. Announces Financial Results for First Quarter 2007
  • TRADE NEWS: Agilent Technologies' BSIM3 Model Extraction Package for CMOS Modeling Foundries Now Available
  • Silicon Motion Announces Agreement to Acquire FCI, Inc.
  • Xilinx and port GmbH Demonstrate Industry's First Complete Solution for ETHERNET Powerlink  
  • TI Advances Communications, Imaging and Instrumentation with Industry's Highest-Performance Dual and Quad ADC Family  
  • Integration Associates Unveils Its latest EZRadio(TM) Receiver - IA4322  
  • Xilinx Enables Miranda Technologies Kaleido-X Multi-Image Processor  
  • Handshake Solutions releases clockless interconnect IP  
  • ARC Building Advanced CPF-Enabled Flow to Lower Power Consumption of Its Configurable Subsystems and Cores

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    -- Jack Horgan, EDACafe.com Contributing Editor.