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January 28, 2008
Fireside Chat: Rick Lucier & Jim McCanny
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Welcome to 2008. At this writing, the global markets are things of terrible beauty – worldwide, they’re down, down, down, with the Dow Jones this morning hitting a 52-week low, along with the NASDAQ. After spending yesterday’s Martin Luther King holiday watching the rest of the world’s indices get trashed, the NYSE dropped a ferocious 400+ points this morning, just past the opening bell, but then rebounded somewhat on news of an emergency rate cut from the Fed.

Meanwhile, anybody interested in EDA this morning would see that CDNS is mimicking the DJI and trading at a 52-week low, as is SNPS and MENT. Not so, however, for LAVA. What’s up with that? Why is it, that despite overwhelmingly bad economic news, Magma seems to be laughing in the face of danger? Hopefully, I’ll have a chance to track down the LAVA folks sometime in the next day or so for a chat about their take on that situation. I look forward to exploring the Mystery of Magma. [Editor’s update: The LAVA folks aren’t able to discuss such things, apparently, because they’re on the verge of their quarterly financial update.]

Now, however, it’s time for my monthly installment of EDA Days of our Lives. This month’s edition includes a virtual discussion between Carbon Design Systems’ President & CEO Rick Lucier and Altos Design Automation CEO & Founder Jim McCanny.

Although the two conversations with these gentlemen spanned both space and time, through the magic of modern computing it will appear the discussions took place at the very same hour, next to a roaring fire in a cozy, paneled library. Since it’s colder than the surface of Mars outside pretty much everywhere in North America at this moment, keeping that fireside-chat image in mind during the writing/reading of this piece is a definite attraction. So, put on your smoking jacket and pull up your big wingback chair. I think you’ll enjoy listening in.

I’m grateful for Nanette Collins for arranging my chat with Rick Lucier. I’m grateful to Ed Lee for arranging the chat with Jim McCanny.

Fireside chat: McCanny & Lucier …

Question – Are you enjoying your job?

Jim McCanny – I’ve been here just over 2 years and, yes, definitely – I’m enjoying my job. But that doesn’t mean it wasn’t tough [to get the business] started. But, we feel that even in our short life, Altos has proven what we’re doing has value. We’ve got a good growth path and we feel optimistic about what we’re doing. Hopefully, others feel the same.

What we’re doing is a heck of a lot harder than working at a big company and we do keep long hours at times, but it’s a market that takes a long time to grow. We try to [balance] the grind with the fun.

Rick Lucier – Yes, I am. I’ve been at Carbon for 18 months now, and we’ve really clarified our position in that time. And, we’ve added many key customers and partners. Yes, it’s fun – not necessarily easy, but fun.

Question – What’s up with the market volatility today – does it impact how you do business?

Rick Lucier – No, people panic when things go up and down, but it’s too early to see what’s going to happens – how much of it is emotional. For us at Carbon at this point, it doesn’t really impact us. We’re going to continue to attack our markets and stay on the path we’ve planned for ourselves. Nothing’s going to change that.

Question – Give me the elevator pitch – what does Carbon do?

Rick Lucier – We automatically create system-level models that can be deployed for system-level design. We take Verilog and RTL and automatically develop a model that can be deployed in a virtual system prototype, which can be used by system architects and for pre-silicon software development. We’re attacking the primary bottleneck in EDA and design today – software development.

Question – Jim, what does Altos Design Automation do?

Jim McCanny – What we’re involved in, is taking the models created for devices and converting those to models at the cell level. Those cell-level models can be used for timing signoff, and can be used in the design flow for [looking at] signal integrity.

The old way [design was done], the designer would give the design to the characterization guy, and he would create the models. That was the Black Box theory. But with the Altos tools, we don’t require the designer to tell us anything because our tools can understand the functionality and electrical characteristics of the paths in the circuit.

Question – Is the famous whack-a-mole model too simple to describe the design optimization problem?

Jim McCanny – It may be too simplistic, but in the past designers could make tradeoffs between various design targets [and still achieve design closure]. You could look at the variables and treat them as independent factors [in moving to design closure].

But, when you get down to 90 nanometers and are working to get more components on the chip – working to make things smaller and more portable – you start worrying about leakage power and signal integrity and trying to add in optimization on top of that. You struggle to optimize even those two variables, when there were actually now five variables that need to be optimized – area, timing, power, leakage, and signal integrity.

Basically, optimization and place & route systems focus on making sure you get the timing that you need – but we’re seeing that this methodology no longer works. You can fix the timing, but blow the power. You can optimize for one or two variable, but only get [best guess] success with the others. You have to build in so much margin for your variables [that you don’t get closure anywhere].

Rick Lucier – At Carbon, we take a more holistic look at system-level design, not a traditional look. If you look at traditional hardware companies today versus how they looked, say, 20 years ago – they’ve got 10x-to-20x more software people than hardware people compared to 20 years ago, because that’s where the fundamental bottleneck is today. You look at the high-level problems [being solved] and you see really big gains in shrinking the overall design cycle by attacking the software problems. Without a doubt, those problems are hard to solve, but that’s how we’ve improved the chances of our customers getting to market faster.

So, rather than a whack-a-mole game, I would say that EDA has always been a game of bottlenecks. You look at where there’s a bottleneck in the design and you work to solve it. A successful EDA company solves a bottleneck and puts the solution into an existing design flow. How much you’re able to shrink the design cycle [defines] how successful you are. And that’s the way it’s always been in EDA.

Again, I would say that rather than whack-a-mole, it’s a question of the bottleneck problem. It used to be the hardware, and now it’s the software. By creating models like we do, that can be used at the system-level, we allow for earlier architectural and software tradeoffs to be made – and when you start doing that, 1) you start collapsing the design time, and 2) you becomes more efficient at testing the software and the hardware.

Question – Respectfully, Rick, is that really a new idea?

Rick Lucier – Well, definitely people have been striving for this for a long time. Maybe I’ve been in EDA too long, but it is something that’s been around for a long time. Now, however, the tools are ready to address it and the market is ready to invest – hardware/software co-design. Now there’s a whole host of vendors who are providing virtual prototypes, but the tough part [remains the] modeling. How are you going to model existing and third party IP and accelerate them? Since hardware is becoming more commoditized, more product differentiation is being done in the software, so it’s critical to get an earlier start on the software side of the equation.

Question – Do you think this situation is one that could have been anticipated 10 years ago?

Rick Lucier – Even 10 years ago, people were pushing for hardware/software co-design, but now I think the tools are ready for it. We have a ways to go still, but the market is definitely there. It has come to the realization that there are a lot more software people out there than hardware people, plus there’s a lot more software in electronic products than there was 10 or 15 years ago. So yes, people could see it moving in this direction 10 years ago, but software development wasn’t the critical bottleneck that it is today – returning, again, to that idea of the bottleneck game.

Look at the iPhone. Apple re-deployed many software engineers from other projects to ensure a timely release of the iPhone. That was all about the software issue, not the hardware. And that’s true today for lots of wireless and consumer vendors. Certainly that’s what our customers are seeing, and they’re building methodologies to address the hardware-software challenge. For big companies, what was an R&D project a few years ago is now a formal corporate initiative to develop methodologies to address this area.

Question – Rank the targets for design in order of importance and/or difficulty at 65 nanometers: Area, Timing, Power, Leakage, Signal Integrity

Jim McCanny – That can’t be done on an absolute scale – the ranking of these targets always depends on the market for the end product. [Having said that], signal integrity is usually a lower priority than timing.

Rick Lucier – That question isn’t really relevant to our [business model], but I will say that one of the things our customers do with our product offerings is – in order to get a really good understanding of the power usage in their end product, they need to run the software on it. It’s hard to get accurate power utilization from just a testbench, so we’re seeing a lot of people taking our tools and interfacing with power analysis tools to get a more accurate picture. Of course, that ranking may depend on which vertical [market] you’re talking about, but in the wireless space, for instance, power is critical. So, I would say in answer to your question, ranking the design targets depends on the vertical.

Question – Are the hardware guys providing a lot of CPU power and the software guys needing to catch up – in particular, a reference to multi-core products coming off the line today.

Rick Lucier – I think they are, but it’s challenging. Clearly performance on processors isn’t growing like it used to, although definitely there’s more horsepower via multi-cores.

Utilizing multi-cores depends on the application. Some application fit a multi-core, but it requires a fair amount of retooling. The question is, where do we take advantage of multi-cores in the software stack? Do you solve it at the application level? At the middleware level? Seems like a real opportunity exists to solve it in the middleware and avoid the retooling at the application level.

There’s an opportunity there to do all of this, but it’s hard to look at every application [and develop a solution]. You have to ask, can I parallelize it at all? The answer may be gated by the design data, which may not lend itself to parallelization. So, yes – maybe you could say the hardware guys are ahead of the game, because the cost of “porting” remains quite high, without a general scalable solution.

Jim McCanny – No matter what people may say, the hardware guys can’t just say to the software guys, ‘Here’s your hardware. Now where’s the software?’ It’s a lot more complicated than that. It requires the software guys figuring out how to make the software run faster on the new hardware. [Overall], I think the hardware guys haven’t had enough conversations with the software guys: ‘How are you going to use this? What are your end applications and how will they benefit from this?

Question – How do we re-position the EDA tools to run on multi-core processors?

Jim McCanny –The problems in EDA are not simple, although the development systems are now very cheap. As recently as 5 years ago, you needed a whole campus of servers to [work through the EDA algorithms], plus a whole bunch of PhDs. Now the hardware guys have given the software guys so much CPU power, that there is a lot of potential for new solutions [on the horizon], although it will take a decent amount of time to implement it all.

Rick Lucier – I think everybody in EDA has always known that it’s performance, performance, performance – that’s always been a critical thing in EDA tools. If we can accelerate the performance of our tools by taking advantage of multi-core hardware, clearly we will. But it’s not a simple problem, as I said before. Just because I can parallelize something doesn’t mean it will execute faster. Some place and route algorithms might improve, or some simulations, but it all depends on how you partition between the various processors. How clearly can you isolate things? Clearly it’s something we’re looking at here at Carbon, but you can put a lot of work into it and not realize a payback.

Question – Where is Ground Zero today for EDA tools development? Has it moved from North America to places like India and/or even China?

Jim McCanny – It doesn’t really matter where ’Ground Zero’ is, because I still believe the [bulk of the innovation] comes from startups wherever they’re found. The [folks in startups] are not held up by the baggage of having to support the existing systems [that characterize the Big EDA vendors], or the baggage of the management of the larger organization pulling them in multiple directions.

That’s why the little startups in EDA are so vital to the survival of the industry. And, that’s not to say that the Big Guys don’t come up with ideas, or that every startup is innovative.

Rick Lucier – By and large, development is still centered here in North America, but a fair amount of development has moved offshore – particularly to India, China, Russia and Poland. It’s really all over the place these days as people [continue to] take advantage of where the talent it. The situation is definitely more fluid.

Not so many years ago, people were rushing to do things offshore, and today people continue to push things offshore, but they’re also bringing things back depending on the stage of development. I’d say my gut answer to the question is, Ground Zero is still in North America.

Question – If it’s best in EDA to be near the customer and the customer is moving offshore, doesn’t that push for things to move elsewhere?

Rick Lucier –
Well, the customer is everywhere today. It’s even more widespread than just saying the customer is ‘globalized’. So, you move offshore if you have to be there. In the past, it’s been purely a question of cost and talent, but now it’s cost, talent and the need to be closer to the customer. It just makes sense to have a fair amount of representation. Certainly in India, where we have a fair number of multi-nationals, it’s not just a cost thing today. It’s a question of wanting to be closer to the customer.

Question – Should people be concerned about consolidation in the EDA industry? Is the customer served by one-stop shopping?

Jim McCanny – If what you’re asking is: Are people standardizing on one supplier? The answer is yes. That’s the case, at least, on the surface – but I think it’s more complicated than that. If you need to get a design done, you’re going to go to a specific [tool vendor] to get a specific answer. But, in some major areas that are traditional, particularly in the digital design flow, you’re starting to see there’s not a whole lot of choice between the players, so the customers are just looking for discounts. That’s good news on the buyer’s side, although the solutions may not [be all one could wish for].

There’s one other thing here that comes from my own background in design. When I was a semiconductor engineer in the late 1980’s, we consolidated on Mentor. Then we consolidated on Cadence. Then we consolidated on Synopsys. Then we consolidated on Magma. And that tells you something. You may not actually want to be the preferred provider [for your customer]. The demands of the technology customer [evolve] in a diverse market.

Having said that, the one thing that concerns me is that even though people go in and have this all-you-can-eat deal with their EDA vendor, if a startup can solve the problem, the customer will still go to that vendor. The Big Guy EDA vendor with the all-you-can-eat contract may say, ‘Just give us time to solve that problem for you, and besides the solution is free.’ But, that’s not really the case. The customer will still do the deal with the startup to [get the quicker solution].

[Meanwhile], it’s a challenge for the small startups to stay independent of the flows [from the big EDA vendors]. We’re independent – not biased to a particular flow or tools from a particular player – but in our space, that’s a little less difficult because of the de-facto library formats. However, there’s no standard for statistical models, so we have to work to create that standard – something that can take a lot of time and effort. We’re a part of Si2, and we hope the industry will consolidate to their formats, rather than every tool having its own flavor.

[Ultimately], however, it’s a question of business relationships. We can have a relationship with Company A, and the next thing you know we’re working with Company B. Then [Company A] says, ‘Wait a minute – we though you were our friend!’ It take a little bit of diplomacy and a lot of hard work [on our part] to keep things going.

Question – Does consolidation in the EDA industry make it that much harder for small companies to survive?

Jim McCanny – Small companies need to work closely with their customers and [that costs money]. And your customers need to put up with you as a small company, warts and all.

On the other hand, for the big companies, things are also challenging. There are layers and layers in those organizations – sales, marketing, etc. – which make it hard to react quickly to customer demands. But Big Company or Small Company alike, when the code doesn’t work, the customers bad mouth the EDA vendor and that makes it even tougher to bring innovation to market. Everybody needs to work closely with the customer to get products to the level that can cross the chasm.

[The biggest challenge is always] the innovation. Although, for customers of startups, they [frequently] have a different expectation of the EDA vendor. Maybe those customers are a little gentler [about bugs] than if the tool comes out of one of the big corporate players in EDA. [Problems with tools from big players] always result in comments from the customers like, ‘Those guys really don’t know what they’re doing!’

I’ve seen the big companies try lots of different ways to stimulate innovation, but it’s always a challenge. On the other hand, the ability for a startup to get everyone lined up and focused on what needs to get done, is a process that’s light years faster than at a big company. That’s why the little startups in EDA are so vital to the survival of the industry.

[In the end], we all roll the dice and take a chance, and hope there’s enough distinction between our solution [and the solution from the other vendors] to make ours more responsive, [and to counter the argument from the Big Guys] that if the customer goes with the consolidated deal, they’ll get everything for free.

Question – Same question to you, Rick, should people be concerned about consolidation in the EDA industry? Is the customer served by one-stop shopping?

Rick Lucier – Yes, the EDA industry is maturing a bit. And it does look, at times, like an oligopoly of sorts – an industry undergoing consolidation. You’ve got your Big 3 or Big 4, depending on how you look at it. But, a bigger part of [the question is], how do the EDA companies look at themselves? Do they value market share or market growth?

The big companies look at their market share, and the small companies look at their market growth. So, the question for small companies is, how do you grow your market? The reason I’m so bullish on Carbon is that we’re growing our market by bringing the software content into the design flow and that [translates] to faster time to market for our customers.

Is consolidation bad for the EDA customer? I don’t think so. As a small company, it makes it harder for us in some regards, but in other regards it actually helps. Because, if you’re partnering with the Big Guys in EDA, and not competing with them, you can put together a win-win proposition with them and they’ll help you. And, since there’s not that many of them, if you can leverage that consolidation, you can turn what may look to some as a bad thing, and see it instead as an opportunity for smaller companies to be more nimble. By combining their technology with the big companies, small companies can prove their worth to the big companies and the customers actually benefit.

Question – Rick, I thought I’d get something a little less positive out of you about all of this.

Rick Lucier – [Laughing] I’m seldom accused of being overly positive, but I do believe the situation today [works to the advantage of the small companies in EDA].

Question – Do we want to try to self-fund for as long as possible to prevent the loss of autonomy that comes with VC money?

Jim McCanny – You obviously have to raise money to get started in EDA. Self-funding may be the goal, but the fact is, for only a few companies will that pay off in the long term. I’ve been in big and small EDA companies, and I’ve seen how challenging it is to innovate and bring [those products] to market. Small companies need VCs, because the game changes quickly with each new process technology and you need your tools to track those changes through innovation.

And [again], the industry needs the small companies. I can’t put my finger on any small company in this industry that’s not doing something that’s valuable. And, if they can do something right, someone will pay for their tools and they’ll be successful.

Rick Lucier – That’s actually a double-edged sword: What is the probability of success bootstrapping versus taking money from VCs? There have been some successful companies bootstrapped in EDA, but the majority were venture funded. I’m not looking at any data, but that’s my guess.

If you have big ideas, you need money. You’ve got to go to the VCs and pitch the idea. Yes, angel money, VC money, and so forth, means giving up ownership – but unless you want a ‘lifestyle’ company, you’ve got to look at the probability of success. And you improve that probability with venture funding.

Although you may lose ownership – and it’s often a personal decision of the people who start the company – there’s a difference between losing ownership and losing autonomy. Getting venture funding doesn’t necessarily mean you lose autonomy.

Question – Do you foresee a time anywhere out there where self-assembling systems might provide relief to the design problem?

Jim McCanny – Actually, to some degree that’s what synthesis has been trying to do all along. But as far as completely self-assembling systems is concerned, it would be great if it would work. If you could arbitrarily pick up any logic circuit, create the hardware on the fly, and plug it in – that would be very nice. Certainly, there’s been work going on [in industry and academia] along those lines, but I believe that research has run out of steam somewhat.

Rick Lucier – I think you see the design problem shift more towards the software side as more and more commoditized hardware, third party IP, augments internally developed IP. With the increased use of commoditize hardware you see more and more of the product being differentiated through software. So today, any leading technology product, will include your own IP augmented with third party IP – that doesn’t simplify the design complexity but it may move the bottleneck into the software side.

Question – What are your New Years’ Resolutions, if any?

Rick Lucier – We want to continue to build on the momentum for Carbon, to continue adding big new accounts and expanding on our existing accounts. There’s no magic in building a successful EDA Company – you just have to expand in your existing major accounts and add new ones to the list.

Question – Are you making a call on the Super Bowl?

Rick Lucier – [Laughing] Well, Tom Brady was limping around on a cast this morning, but I’m still going with the Patriots!

The official bios …

* Jim McCanny: CEO & Founder at Altos Design Automation

Prior to Altos, McCanny was the Timing and Signal Integrity Marketing Group Director at Cadence. He was the Vice President of Marketing and Business Development at CadMOS when they were acquired by Cadence in 2001. Before CadMOS, McCanny was Executive Vice President at Ultima Interconnect Technology (which, as Celestry, was acquired by Cadence in 2003), Major Account Technical Program Account Manager at EPIC Design Technology (IPO in 1994), and a Member of Group Technical Staff at Texas Instruments. McCanny has a BS in Math/Computer Science from Manchester, U.K., and has over 25 years experience in EDA. You can learn more about McCanny in his March 2007 interview with Jack Horgan in EDA Weekly.

* Rick Lucier: President and CEO of Carbon Design Systems

Prior to Carbon, Lucier was CEO of Aras Corp., a startup enterprise company in the product lifecycle management market. He has more than 22 years in the EDA industry and served as COO at Innoveda. For several years prior, Lucier held various positions at Viewlogic Systems, Inc., including COO, Group Vice President, Vice President of Product Engineering and Director of Consulting Services. He also served in engineering positions at computer-aided-engineering software and computer companies.

Calendar notes …

* VaST’s Changing the Game – Second in the VaST Innovation Series, this January 31st lunchtime event in San Jose includes a keynote from CMP’s Paul Miller and a panel discussion moderated by Gartner’s John Barber.

* ISSCC 2008 – The IEEE International Solid-State Circuits Conference is “the foremost forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and use to maintain technical currency, and to network with leading experts.” This event, companion to December’s IEDM, is the conference that separates real engineering from child’s play. Wusses need not apply. It’s happening in San Francisco, February 3rd to 7th.

* DesignCon 2008 – The IEC’s 12th annual conference, happening February 4th to 7th in Santa Clara, will cover the waterfront, topic-wise: architectural and functional design, verification, DFM, PCB and package design, jitter, noise, power, RF, SI, and the host of business issues that arise in making all of that engineering come true.

* EDAC CEO Forecast & Industry Vision Panel – The Big EDA guns will be out in force at the EDAC Watering Hole on February 7th in Santa Clara. Come hear MIPS’ John Bourgoin, Synopsys’ Aart de Geus, Cadence’s Mike Fister, Jasper Design’s Kathryn Kranen, Denali Software’s Sanjay Srivastava, and Mentor Graphics Wally Rhines prognosticate about the next 12 months in your industry. What these guys don’t know, may not be worth knowing.

* CMSE 2008 – The 12th annual Components for Military & Space Electronics Conference & Exhibition is taking place in San Diego from February 11th to the 14th.

* DVCon 2008 – Organizers call this gathering “the premier conference for functional design and verification of digital electronic systems.” They also say there’s been a 30% increase in exhibitor participation compared to 2007. DVCon is happening February 19th to 21st at the DoubleTree Hotel in San Jose. Mentor Graphics’ Wally Rhines is giving the keynote. ESNUG’s John Cooley is moderating his annual CEO circus.

* MUSIC Silicon Valley – Organizers say the Magma Users Summit on Integrated Circuits is “dedicated to providing an open forum for users to share and exchange ideas on how they use Magma solutions to meet the challenges of IC and SoC design.” It’s happening February 27th and 28th in Santa Clara.

* Avionics08 – Organizers say this is “the leading Conference and Exhibition for Military & Civil Avionics,” and includes topics such as Military Response to tomorrow’s airspace systems, F-35 Joint Strike Systems, and Eurofighter Typhoon Avionics. It’s happening March 5th and 6th in the Passenger Terminal of the Amsterdam Airport.

* DATE – The 11th annual Design, Automation & Test in Europe conference is taking place March 10th to 14th in Munich. Organizers say they have received a record number of paper submissions for the 2008 event, particularly in the areas of embedded systems and software. Lots of folks you know will be there.

* ISQED 2008 – The International Symposium on Quality Electronic Design “emphasizes a holistic approach toward electronic design by accelerating cooperation among the IC design, EDA, semiconductor process technology and manufacturing communities.” It’s happening March 17th to 19th in San Jose.

* Intellectual Property Symposium 2008 – Per Organizers at CMP: “This inaugural symposium is the place where those in the technology and legal arenas will meet in a communal setting to learn, analyze and engage in the issues that the electronics industry faces.” The Conference will run in San Jose on April 15th and 16th, communally concurrent with ESC.

* ITC2008 – The IEEE International Test Conference will be happening October 28th to 30th in Santa Clara. If you want to submit a paper for consideration, hurry. You’ve only got til February 15, 2008.

News of the cool …

* Catalytic Inc. announced the company has changed its name to Agility Design Solutions Inc. Per the Press Release: “The name change reflects the dramatic expansion in company size, product offering, geographic reach and company vision resulting from the recent merger of Celoxica’s ESL business with Catalytic.”

I had a chance to speak by phone with Agility President & CEO Dave Burow several weeks ago at the time of the acquisition of the Celoxica ESL assets by what was then Catalytic.

Dave told me, “We feel very lucky, because when we became aware that Celoxica had publicly announced their focus to accelerate toward applications such as the life sciences, oil & gas, and finance, we through it would be great if we could hook up with the guys [at Celoxica] who had the same customers and were [addressing] the same kinds of applications that we’re addressing.

“Our customers are always looking for ways to run their algorithms faster, so it was a great fit [between Celoxica and Catalytic]. We stayed [closely] involved with the situation at Celoxica, and as some of the other companies bought other parts of the company, we were able to put that part of the Celoxica product line together with the Catalytic product line to create a focus on algorithmic development and implementation. It’s pretty rare for a private company like Catalytic to get another product line as big and as established as Celoxica’s ESL product line. There are so many new applications [that come out of this move] and there are so many potential new customers, we’re very excited about all of this!”

* Xilinx announced that Moshe Gavrielov has been appointed President and CEO, succeeding Willem Roelandts, who will remain as Chairman of the Board. Per the Press Release: “Gavrielov will be the third Xilinx CEO in the company’s 24-year history, and brings 30 years of executive management and engineering experience with semiconductor and software companies to Xilinx. Most recently, Gavrielov served as Executive Vice President and General Manager of the Verification Division at Cadence Design Systems. Before that, Gavrielov spent seven years as CEO of Verisity, where he grew the company from a $4 million start-up, taking it through its IPO in 2001 to a $70 million publicly-traded company, and ultimately to its acquisition by Cadence in 2005.”

* SynTest announced that company founder Dr. L.-T. Wang has been named an IEEE Fellow. Per the Press Release: “Wang founded SynTest in January 1990. Since then, Dr. Wang has led the company to grow to more than 50 full-time employees and 200 customers worldwide. Along with overall management responsibility for worldwide operations, he is also responsible for defining SynTest's technology roadmap. Prior to founding SynTest, Dr. Wang had worked at several technology companies, including Intel and Daisy Systems. Dr. Wang has published more than 40 technical papers and currently holds 16 U.S. and European patents in the area of Test Generation, BIST, and DFT. He is also a co-editor and co-author of: VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007). He received his MSEE and EE PhD degrees from Stanford University, and his BSEE and MSEE from National Taiwan University, Taiwan.“

* Northrop Grumman Corp. announced a new “world record” for transistor speed with what the company says is “an ultra-fast device that will provide much higher frequency and bandwidth capabilities for future military communications, radar and intelligence applications.” Per the Press Release: “The company has produced and demonstrated an indium phosphide-based High Electron Mobility Transistor (InP HEMT) with a maximum frequency of operation of more than 1,000 gigahertz, or greater than one terahertz.” The Northrop results were showcased at IEDM in Washington, D.C., in December 2007.

* Samsung Electronics Co., Ltd. announced “the world’s fastest memory, a GDDR5 (series five, graphics double-data-rate memory) chip that can transfer data at six gigabits per second, which is more than four times faster than that of memories in state-of-the-art game consoles today.”

* X-FAB Silicon Foundries announced that the Brazilian-government-backed Excellence Center for Advanced Electronic Technology [CEITEC] has established a licensing agreement with X-FAB for semiconductor manufacturing. Per the Press Release: “CEITEC will license X-FAB’s advanced 0.6 micrometer process technology called XC06, enabling CEITEC to establish the first commercial CMOS semiconductor front-end manufacturing operation in Brazil … CEITEC is part of a Brazilian-government-sponsored effort to develop a domestic microelectronics industry … CEITEC’s 0.6 micrometer process will be fully compatible with X-FAB’s XC06 process.”

* IMEC says it is “setting foot in Taiwan.” Per the Press Release: “IMEC has officially established IMEC Taiwan in the Hsinchu Science Park. IMEC Taiwan initially starts as a representative office but is expected to grow into an R&D center within the coming 6 months. IMEC Taiwan aims to set up a win-win situation by facilitating the access for Taiwanese semiconductor companies to IMEC's R&D programs and tap into the local high technology skills … IMEC intends to reinforce its collaborations in Taiwan by focusing on semiconductor process technology research with foundries, on IC and system design with companies and academia, on dedicated training, on facilitating the interaction between Europractice IC service and the Taiwanese foundries for low-cost IC prototyping and small volume production, and on developing heterogeneous process technologies for fablite and fabless companies.”

* AtopTech was launched as a new EDA company and announced a product for the physical design of ICs at 90 nanometers and below. Per the Press Release: “ATopTech Inc., was formed in late 2003 and development on the EDA software was begun in 2004. The company has raised $14 million in two rounds of funding. Investors include the founding team, Acorn Campus Fund II, VCEDA, iD Innovation, Inc., and H&Q. Founders include Don-Min Tsou, President; and Kaiwin Lee, Executive Officer. Rounding out the executive team are Ping-San Tzeng, Chief Architect; Eric Thune, Vice President of Sales and Marketing; and Eddie Araki, President of ATopTech KK in Japan. Members of the Board of Directors are Don-Min Tsou, Kaiwin Lee, and Wu-fu Chen, managing member and co-founder of Acorn Campus.”

Do the Venn Diagram …

* Cadence Design Systems and Mentor Graphics announced the Open Verification Methodology (OVM). Per the Press Release: “Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge from the OVM website.”

* Magma Design Automation, Mentor Graphics, and Synopsys announced the three companies are now delivering low power EDA tools based on the Accellera-developed Unified Power Format standard, UPF 1.0. Per the Press Release: “This includes a broad range of implementation and verification products from the three companies. This new UPF product support further enhances key low power capabilities in the companies' tools while expanding industry interoperability, especially when compared to other available options.”

* Cadence Design Systems announced that Japan's STARC [Semiconductor Technology Academic Research Center] released its “next-generation ultra low-power” PRIDE reference flow V1.5, that the organizations say incorporated the Common Power Format based on Cadence’s Low-Power Solution. Per the Press Release: “This reference flow also includes key litho-aware DFM technologies from Cadence.”

Additional recent news …

* Acceleware Corp. and Synopsys announced “a new hardware solution that enables up to 20-times faster electromagnetic simulation of optoelectronic devices such as CMOS image sensors.” Per the Press Release: “[The solution] links Synopsys' … TCAD Sentaurus Device simulation software and Acceleware's ClusterInABox Quad Q30 workstation, and enables an order-of-magnitude speed-up of the high accuracy finite-difference time-domain (FDTD) electromagnetic modeling algorithm used in Sentaurus Device.”

* ACE (Associated Compiler Experts) announced that ClearSpeed Technology used ACE’s CoSy compiler development system in the development of “a high-performance, parallelizing compiler for [ClearSpeed’s] accelerator product line that includes the CSX600, a multi-threaded array coprocessor … The CSX600 is a massively parallel processor architecture with a SIMD data path with 96 processing elements, each equipped with a dual 64-bit FPU, local registers and local memory.”

* Actel Corp. announced its Icicle Kit, which the company says leverages the Actel 5-microwatt IGLOO FPGA. Per the Press Release: “The $99 kit allows designers to easily and rapidly program, evaluate and modify their low-power IGLOO-based portable designs. Powered by a rechargeable lithium-ion battery, the 1.4” x 3.6” Icicle evaluation board consumes less than one-seventh the power of competitive FPGA development solutions in a design the size of a small cell phone.”

* Agilent Technologies says Maspro Denkoh Corp. has purchased multiple licenses of Agilent's Genesys and Momentum GX software to develop TV-receiver and satellite-broadcast equipment. The agreement between the companies includes an optional upgrade to other Agilent EEsof EDA products.

* In addition, Agilent EEsof EDA announced its GoldenGate Plus product, which the company says is for RFIC simulation, analysis and verification. Per the Press Release: “The product line … combines the high-capacity GoldenGate simulator, acquired from Xpedion in 2006, with a customizable data display, EM simulation and system-level design and simulation.”

* Altium announced Gerry Gaffney has been appointed Senior Vice President and General Manager, for the Americas. Previously, Gaffney spent 11 years at Cadence Design Systems. Prior to Cadence, he was with EDS in the U.K.

* Altium also announced the recent appointment of Jay Cao as Regional Director China, based in Shanghai, and Anand Shankaran as Chief People Officer for Altium worldwide, based in Sydney.

* Ambric, Inc. announced the Ambric Am2045 GT video reference platform, which the company says is based on the Ambric Am2045 massively parallel processor array device with 336 RISC processors. Per the Press Release: “Ambric’s reference platform has been integrated into new, yet-to-be announced advanced, high-definition, video-processing products and software from Pyro AV by ADS Tech and Sorenson Media. These video-processing products will address the video productivity challenges of over one million users of professional and prosumer video editing and authoring software.”

* Ambric also announced the “transparent integration” of the Ambric Am2045 GT video acceleration reference platform with Adobe Premiere Pro CS3 and After Effects CS3.

* AtopTech announced a multi-million dollar, multi-year contract with Broadcom Corp. Per the Press Release: “Broadcom will use ATopTech’s next generation place and route software for designing integrated circuits at 65nm and below. Broadcom’s first chip using ATopTech’s software has already taped-out and had first pass silicon success.”

* AWR announced that December 2007 marked the company’s 10th year of business. Per the Press Release: “AWR began servicing its first customer on December 10th, 1997 with one seat of software. Since then, the company’s customer base has grown every year, resulting in over 20,000 active users in 2007.”

* Berkeley Design Automation Inc. announced that SiPort Inc. selected Berkeley Design’s Analog FastSPICE circuit simulator. The companies say this choice will “enable SiPort's designers to verify their digital multimedia broadcast receiver designs with true SPICE accuracy in a fraction of the time required by traditional SPICE tools.”

* Cadence Design Systems, Inc. announced that Toshiba Corp. used Cadence’s Virtuoso to provide its analog and mixed-signal chip designers an “easy-to-use and accurate reliability analysis flow.” Per the Press Release: “Toshiba and Cadence worked together to implement Toshiba's advanced reliability models into Virtuoso UltraSim simulator using the UltraSim Reliability Interface and tested the results, resulting in the selection of the UltraSim simulator.”

* Calypto Design Systems announced its SLEC (Sequential Logic Equivalence Checker) System-HLS, which the company says is designed to verify high-level synthesis (HLS) output. Per the Press Release: “SLEC is the semiconductor industry’s only functional verification solution to formally verify equivalence between ESL models and RTL implementations. SLEC System-HLS tightly integrates SLEC System into HLS design flows by automating setup and supporting HLS language extensions, such as Algorithmic C datatypes from Mentor Graphics and System C Modular Interfaces from Forte Design Systems. SLEC System-HLS comprehensively verifies the RTL code synthesized from system-level models without the need for writing testbenches or running simulation.”

* Carbon Design Systems announced a $6 million round of funding. Investors include Commonwealth Capital, Flagship Ventures and Matrix Partners. Also in the Press Release: “Carbon will move to new corporate headquarters in Acton, MA, in late January to support its growing staff.”

* Chip Estimate Corp. announced that Synopsys has joined the Chip Estimate Prime IP Partner Program.

* Chipidea announced that its USB high-speed physical layer (PHY) IP has been certified on 65-nanometer and 90-nanometer process technologies available from Chartered Semiconductor Manufacturing Ltd.

* CoFluent Design announced the release of the CoFluent Reader, which the company says is a model viewer and player. Per the Press Release: “CoFluent Reader allows browsing and viewing freely graphical models captured with CoFluent Studio, CoFluent Design’s ESL visual architecture development environment. In addition, simulations of models can be played back for observing predicted behavioral, real-time and performance results.”

* CoWare announced a collaboration with STARC [Semiconductor Technology Academic Research Center] in Japan to support CoWare’s open SystemC modeling library.

Per the Press Release: “APIs [have been developed] for the creation of highly reusable virtual platforms for architecture design and software development within CoWare’s ESL 2.0 environment using STARC’s new transaction-level (TL) modeling guideline … The new TL Modeling Guideline … is based on industry standards from the Open SystemC Initiative (OSCI), the IEEE 1666-2005 Standard for SystemC, and established practical de-facto standards for transaction-level model interoperability as recommended by the System Level Design Group of STARC. This work includes participation by engineers from leading companies driving the adoption of ESL design methods in Japan, including NEC Electronics, Oki Electric Industry, Renesas Technology, Sony, and Toshiba.”

* edXact SA announced a distribution agreements with EDA Sales, Inc. in California and WIN Technology in Korea. Per the Press Release: “This will strengthen the company’s expansion into key regions for the semiconductor industry.”

* Elliptic Semiconductor and Micronas USA, Inc. announced that “Micronas USA has licensed the digital rights management (DRM) Elliptic security solution for use in its SoCs aimed at consumer electronics.”

* EVE and CoWare announced an alliance, which the companies say will provide “an integrated approach that ties hardware/software co-verification from EVE with SystemC virtual platforms developed with CoWare’s ESL 2.0 solutions. This link between two production-proven design flows, made possible through standard transaction-level interfaces, will reduce overall development time for multi-core/multi-application SoCs … This is accomplished by co-executing RTL blocks in ZeBu and SystemC transaction-level platform in CoWare Platform Architect.”

* The College of Nanoscale Science and Engineering of the University at Albany in New York and IMEC in Belgium announced plans to jointly perform extreme ultraviolet lithography experiments in order to accelerate the introduction of EUVL into manufacturing. Per the Press Release: “The first set of collaborative experiments will be carried out at CNSE's Albany NanoTech Complex, with future joint studies to be conducted at CNSE and IMEC, depending on throughput and/or availability of the tools. This groundbreaking collaboration between CNSE and IMEC will also involve scientists from IBM and ASML, which has built the world's first full-field EUVL R&D tool, the Alpha Demo Tool. The majority of activities will focus on the advanced imaging capabilities of the EUVL system, with additional effort devoted to the understanding of new materials and various aspects of equipment technology.”

* Hifn announced its Express DS 255, which the company describes as “the industry’s highest-performance, lowest-power and smallest form-factor data security card … The Express DS 255, easily handles today’s encryption requirements and enables the next-generation network security applications.”

* Hynix and MunEDA announced that Hynix licensed MunEDA's WiCkeD DFM-DFY analysis and optimization tool suite for use in Hynix's Analog Mixed-Signal Design & Foundry Flow.

* Infiniscale SA announced a distribution agreement with IVIS Co. Ltd., a Japanese distributor for EDA products. Per the Press Release: “IVIS was chosen on its reputation for building strong customer relationships and delivering compelling new EDA tools to the Japanese market.”

* IPextreme announced that “select IP cores are now available for purchase through the new online marketplace, the Core Store … Core Store products come fully packaged in an easy-to-use encrypted format with support available as an optional purchase item.”

* IPextreme also announced the appointment of Kazuhiro Ogawa as President of IPextreme Japan. Ogawa has 28 year’s experience in high tech, working at Tokyo Electron Ltd., Fluent Inc., and Nihon Synopsys Co. Ltd.

* JEDA Technologies announced its NSCvCC code coverage product for C/C++ and SystemC designs, which the company says is intended for model developers, platform developers, system designers, and architects. Per the Press Release: “NSCvCC rapid code coverage checking helps to measure IP model quality and identifies code which has not been fully exercised in testing … NSCvCC measures the comprehensiveness of your verification suite, improving quality and productivity and reducing risk.”

* Magma Design Automation announced its Talus QDRC, which the company describes as “a physical design verification product that improves productivity and time to market for 65- and 45/40-nanometer designs by identifying and correcting design rule violations during implementation … Talus QDRC decreases overall design costs by addressing DRC problems before they delay design tapeout.”

* Mentor Graphics announced new technology in its Olympus-SoC P&R product that the company says will accelerate signal integrity closure and improve manufactured silicon reliability. Per the Press Release: “The Multi-Corner, Multi-Mode (MCMM) capability of Olympus’ Static Timing Analysis (STA) engine concurrently computes delay shift and glitch for any number of mode/corner scenarios in a single pass. MCMM analysis [addresses] reliability issues such as crosstalk delay, glitch, power, and electromigration while reducing the time to achieve design closure. The Olympus-SoC product’s detailed routing and optimization engines have been enhanced to help eliminate SI violations concurrently over all variation scenarios.”

* Mentor Graphics also announced the third generation of its TestBench Xpress, which the company says “eliminates the traditional barriers of adopting hardware in-circuit emulation for system-level integration. When used in conjunction with Mentor’s Veloce family of hardware assisted verification products, TBX provides a software based, cost-effective and efficient way to perform hardware-software co-verification for embedded systems.”

* Mentor Graphics also announced an extension to its ESL synthesis flow that the company says, “enables users to implement even higher performance DSP hardware than previously achievable with Catapult for Xilinx devices … The result is designs that operate 50-80 percent faster than results previously achieved by any high level synthesis tool.”

* Mentor Graphics announced, as well, that Fujitsu Ltd. has added Catapult C to its standard ASIC design kit. Per the Press Release: “A number of ESL synthesis tools were assessed in order to meet Fujitsu’s stringent requirements for quality standards.”

* MIPS Technologies announced that Entropic Communication has licensed “the MIPS32 24Kc synthesizable processor core for its next-generation broadband and residential gateway applications.”

* Nangate and Ponte Solutions announced “a tight product integration that will help customers deal with the impact of process variation and design for yield.”

* OCP-IP announced a new debug specification has gone to member review. Per the Press Release: “The specification details an approach to a standardized OCP-bus compliant debug interface. The debug solution, an optional OCP port, implements a debug interface socket that can be added to all cores and IP blocks. The specification supports a uniform method of on-chip system analysis and access to embedded information at the core, multi-core, and systems levels.”

* OneSpin Solutions GmbH announced its 360 EC-FPGA equivalence checker, which the company calls “the industry’s first sequential equivalence checking solution dedicated to and priced for the FPGA market … Formerly an extension of OneSpin’s established 360 EC-ASIC equivalence checker, 360 EC-FPGA now is packaged stand-alone and priced for broad application in the FPGA market. OneSpin also has extended 360 EC-FPGA’s support to include all Altera Stratix and Cyclone FPGAs, and HardCopy; most Xilinx Spartan and Virtex products; and the Synplicity Synplify Pro synthesis flow – including gated-clock conversion.”

* OneSpin Solutions also announced the addition of a standard assertion language link to its 360 Module Verifier solution. Per the Press Release: “The link opens an additional gateway to complete, gap-free functional verification for companies invested in assertion-based verification (ABV) … Using 360 MV, they can exhaustively check and debug both existing and new SystemVerilog Assertions and Open Verification Library assertions. [Among new features]: Assertions can be written in-line or in a separate file and linked to the design-under-verification by means of “bind” statements. This allows users to either instrument the RTL code or write additional assertions files to capture and verify DUV functionality, and integration conditions.”

* Ponte Solutions announced an updated version of the company’s YA System, version 0801, which the company says includes new defect analysis capabilities and enhanced features. Per the Press Release: “This new YA release can now analyze butted contacts, diffusion contact to gate shorts, source-drain shorts, and isolated contacts and vias. In addition, Ponte has enhanced the ease of use for its embedded memory analysis capabilities.”

* Real Intent, Inc. announced today that Carol Hallett has been named Vice President of Worldwide Sales. Prior to joining Real Intent, she was Vice President of North American Sales at Tharas Systems, which was acquired by EVE.

* Sagantec announced it has “enabled MathStar, Inc. to successfully port and optimize its high-performance Field Programmable Object Arrays (FPOAs) that perform at clock rates up to 1 GHz … Using Sagantec tools, Mathstar reused its 0.13um production-proven FPOA design and significantly shortened its new 90-nanometer technology implementation.”

* Silicon Canvas and Synopsys announced the integration of Silicon Canvas' Laker schematic capture and layout environment with Synopsys' Hercules Physical Verification Suite (PVS). Per the Press Release: “Customers using Laker and Hercules PVS can now seamlessly navigate and view the design and electrical rule checks (DRC, ERC) and layout versus schematic (LVS) errors using Hercules VUE with the Laker environment.”

* Simucad Design Automation announced that Elpida Memory Inc. has standardized on Simucad’s SmartSpice for analog simulation.

* Stratosphere Solutions Inc. announced that Stone Pillar Technologies, Inc. has become as a member of its ICTrust Partnership Program. Per the Press Release: “Under terms of the partnership agreement, the companies have integrated Stone Pillar’s TestChipBuilder with Stratosphere Solutions’ StratoPro silicon IP platform to improve parametric yield at 45 nanometers and below.”

* Synplicity announced that Synplify Premier release 9.0, which the company says has been “optimized for Xilinx Virtex-5 FPGAs … This latest release extends the graph-based physical synthesis technology which has been implemented for Xilinx Spartan-3, Virtex-II Pro and Virtex-4 FPGAs for more than two years. Synplicity also announced it has extended these benefits to FPGA designers targeting Altera Stratix-III, Stratix-II and Stratix-II GX FPGAs, through the company's Synplify Premier Beta Program.”

* Synopsys announced “the qualification and immediate availability of the Synopsys Star-RCXT parasitic extraction solution for TSMC's 45-nanometer process technology. Per the Press Release: “Altera is now deploying Synopsys' Star-RCXT as the preferred extraction tool for its 45-nm design sign-off flow.”

* Synopsys also announced that IC Compiler was used in a 45-nanometer SoC device from Matsushita Electric Industrial Co., Ltd., and is entering volume production. In addition, Matsushita used Synopsys' Design Compiler for RTL synthesis, and PrimeTime SI timing analysis solution and Star-RCXT extraction tool for silicon-accurate sign-off.

* Synopsys also announced PrimeTime 2007.12, and says it includes: “broad improvements in design data reading and linking, intelligent disk caching, incremental timing updates and fine tuning of algorithms have resulted in an average 2X runtime improvement and 33 percent memory reduction over the 2006.12 release while maintaining golden signoff accuracy.” The Press Release also says the new release has been endorsed by AMD, RMI Corp., and “several other semiconductor companies.”

* Tensilica announced that it has added support for Avnet's Xilinx Virtex-4 LX200 Development Kit for high-speed hardware-based simulations of Tensilica’s Xtensa configurable and Diamond Standard processor families.

* The MathWorks and Green Hills Software, Inc. announced Embedded IDE Link MU, which the companies says is “a new product from The MathWorks for Model-Based Design, that automatically deploys code generated from Simulink models into the Green Hills MULTI IDE, enabling seamless execution on a wide range of embedded microprocessors, including the Freescale Power Architecture.”

* Triad Semiconductor, Inc. and Arrow Electronics announced a joint effort to provide mixed-signal, via-configurable array ASICs. Per the companies, “Under their agreement, Arrow will distribute and provide technical sales and support for Triad’s mixed-signal ASICs, and Triad will become the first dedicated analog ASIC provider in Arrow’s portfolio of offerings.”

* Triad Semiconductor also announced its first subsidiary, Triad MDG, Inc. in Montreal, under the direction of General Manager Richard Prescott. Per the Press Release: “It expands Triad’s design operations and offers both advanced internal analog IP development and design, as well as external sales and application engineering support for the Canadian market.”

* UMC announced it has been named the Number One semiconductor company in Taiwan in the Clean & Green (C&G) Watch 2007 report conducted by the Asian Corporate Governance Association and CLSA Ltd. Per the Press Release: “The C&G Watch 2007 surveys and ranks environmental awareness of major Asian enterprises from top executives.”

* X-FAB Silicon Foundries announced “progress in transforming” the company’s Sarawak, Malaysia, facility into an analog-mixed/signal foundry operation. Four processes have been transferred and a new 0.18-micron technology added at the facility. Processes transferred include two 0.6-micron processes and two 0.35-micron processes. Per the Press Release: “Companies using X-FAB’s existing 0.6- and 0.35-micrometer process platforms can reuse their current design IP and maintain their current design environments.”

* Xilinx announced it has added three devices and small form factor packaging to its 65-nanometer Virtex-5 LX and LXT FPGA platforms including, “the addition of the Virtex-5 LX155 device to the logic-optimized LX platform, and the addition of the LX20T and LX155T devices plus a new small footprint 19mm FF323 package to the Virtex-5 LXT platform with low power transceivers.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.