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Title : Conformal Logic Equivalence Checking (LEC)
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Date : 28-Oct-2006
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Downloads : 950

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This tutorial provides a quick getting-strated guide to Cadence Conformal logic equivalence checking. The basic flow is to input both an RTL netlist and a synthesized netlist and then have Conformal check whether both netlists are equal. Think of it as an LVS for Verilog. This is a powerful tool to get a formal proof that the output from Synthesis matches the original RTL code without having to run simulation
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