Aldec's patented technology incl. RTL Design/Simulation, Embedded, HW-Assisted Verification, SoC/ASIC Prototyping, DRC, CDC Verification, IP Cores, DO-254 & Mil/Aero solutions. Learn more
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LIVE WEBINAR:
    UVVM - A game changer for FPGA VHDL Verification 

Aldec and Bitvis to present a complete verification solution for VHDL users consisting of a high-performance RTL simulator and a component-oriented VHDL environment. 

EU TIME ZONE

Time: 3pm - 4pm (CET)
Thursday, November 17, 2016
Register Today!

US TIME ZONE

Time: 11am - 12pm (PST)
Thursday, November 17, 2016
Register Today!

Related Blog: FPGA VHDL Verification
How can we do this faster and with better quality - at no extra cost?
By Espen Tallaksen , Bitvis Managing Director and Founder

Webinar Abstract:

In this webinar, we will introduce UVVM methodology with VHDL Verification Components for a ultra-fast, ready-for-reuse simulation solution. Attendees will learn more about the powerful Riviera-PRO User Interface with robust debugging and analyzing capabilities for validation of design under test simulation results. 

The webinar includes live interactive Q&A participation for attendees with Bitvis Founder and director, Espen Tallaksen, and Riviera-PRO Product Manager, Radek Nawrot. 
 

Agenda

  • Verification criticality and efficiency enablers 
  • Introduction to UVVM Utility Library 
  • Bus Functional Models (BFMs) in the nutshell
  • Cycle related bugs - a difficult to detect threat
  • Architecture is key to Efficiency and Quality
  • VHDL Verification Components
  • Writing a test sequencer for everyone
  • Verification of corner cases – value and cycle related 
  • Efficient debugging
  • Enabling Quality, Efficiency AND Reuse
  • Simple Demo of a Dual UART testbench
  • Analyzing my code – Outline in action
  • Why do I need Contributors?
  • Advances techniques on Waveform
firstaider
 
Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Embedded, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
 
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