You are receiving this email as an Internet Business Systems Subscriber on behalf of Blaze DFM, Inc. =============================================================================== Reduce Leakage Power with Blaze MO(TM) Reduce leakage power by 20% or more. Cut leakage variability in half. You may think that you are already doing everything possible to reduce leakage power by using: multi-Vt libraries, header/footer sleep switches, voltage islands, transistor body biasing. We can help you to reduce leakage power even more. Blaze MO offers the following benefits: * Reduce leakage power by 20% or more on digital CMOS designs * Cut leakage variability in half * No performance hit * No schedule hit * Guaranteed timing closure * Can be used on existing or in-process designs * No change to architecture, libraries, logic design, or layout * Fully compatible with, and additive to, the leakage reduction techniques mentioned above * Plugs into any existing design flow * Only one mask (poly) is affected * Supported by major foundries Please contact us for more information on how you can reduce leakage power on your designs today. Request more information about Blaze MO Here are some customer-written articles on how they are reducing leakage power with Blaze MO. Article: Leakage Power Optimization for a Wireless Comms SoC, EDA Tech Forum 12/06 Article: Leakage reduction in SOCs using gate-length biasing, Solid State Technology 9/06 Article: Leakage Power Reduction in a Mobile Baseband Processor, Chip Design 7/17/06 =============================================================================== You are subscribed as [_EMAIL_]. If you no longer want to receive news from our EDA sponsors but want to continue receiving other EDA newsletters, please visit Otherwise, if your email client supports HTML, please change your format preference to "HTML" for the best viewing experience. To change your personalized CafeNews mailing subscription, go to Copyright (c) 2020. Internet Business Systems, Inc. All rights reserved