The Cadence® Xcelium™ Multi–Core Simulator is a third–generation SystemVerilog simulator that shortens simulation time by breaking the design dependencies into independent parts and then simulating those parts on parallel cores of a server. The effect is a significant acceleration of simulation across designs that are both active and large. The Xcelium Multi–Core Simulator supports full timing annotation, making it also useful for long–latency, high–activity, functional gate–level simulations.
In this webinar, our experts will introduce you to the Xcelium Multi–Core Simulator and present some benchmark results. You will also learn how to qualify functional vectors using the Xcelium Single–Core Simulator and how to get started. In addition, we will share a customer experience case study.
Date and Time:
Wednesday, May 26, 2021
8:00 AM PDT/ 11:00 AM EDT/ 6:00 PM CET