EVE and Synopsys are happy to invite you to the “Billion Cycle Challenge” technical seminar
Free Half-Day Technical Verification Seminar

San Diego, Jan 18 (9am - 1pm)

Debug device drivers, extract RTL waveforms, boot Linux, set HW/SW breakpoints
Designers of H.264 graphics chips need to simulate hundreds of conformance streams to make sure that the chip is ready to ship.

In the wireless handheld SOC space, firmware is key.  Ultimately, the device must boot Linux and run a Java application on its LCD screen.

Designers of network routers need to stress their chips through pseudo-random traffic to benchmark key performance metrics, such as packet drop rate.

All these tasks have one thing in common:  they require billions of cycles of simulation.  Until designers realize that they can’t manage billions of cycles like any other simulation, they hit a wall called the “Billion-Cycle Challenge.”

Space at this must-see seminar is limited, so  REGISTER NOW HERE

This seminar is co-sponsored by


Seminar Schedule
8:45am - 9am
Registration, Breakfast
9am - 9:45am
Debugging billion-cycle simulations: using a multi-level approach combining software debug of embedded applications with hardware debug
9:45am - 10:15am
A step-by-step guide on building system-level testbenches using virtual components and accurate transaction-level modeling
10:15am - 10:30am
10:30am - 11am
Guest speaker: experiences in overcoming the billion cycle challenge (speaker is different for each city)
11am - 11:30am
Live demo: see the actual debug of a Linux boot sequence, when chasing HW/SW bugs in a peripheral device. Is it a software bug or a hardware bug? How can the HW and SW teams work hand-in-hand?
11:30am - 11:45am
The latest ARM-based SOCs present new verification challenges. Learn about ARM’s newly announced co-emulation strategy that supports the latest processor advances.
11:45am - 12:15pm
Development of complex SoC requires comprehensive RTL verification, with easy connections to early virtual prototypes as well as emulation to facilitate continuous hardware/software validation.
Learn how the VMM methodology can enable a single transaction-level verification environment to be used during all stages of the RTL development process.
12:15pm - 12:45pm
Who should attend:
- Hardware designers and managers in charge of verification and validation

- Firmware and software engineers that need pre-silicon models and prototypes
2518 Mission College Blvd
Santa Clara, CA 95054
(408) 855-3200

You are registered as: [_EMAIL_].

CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe from EDACafe.com sponsor newsletter.

Copyright © 2020, Internet Business Systems, Inc. — 25 North 14th Steet, Suite 710 San Jose, CA 95112 — +1 (408) 882-6554 — All rights reserved.