You are receiving this email as an Internet Business Systems Subscriber on behalf of EVE =============================================================================== EVE and Synopsys are happy to invite you to the "Billion Cycle Challenge" technical seminar. Free Half-Day Technical Verification Seminar: Oct 16, Boston Oct 17, Ottawa Oct 18, Austin Oct 30, San Diego Oct 31, Santa Clara Learn to Debug device drivers, extract RTL waveforms, boot Linux, set HW/SW breakpoints... Designers of H.264 graphics chips need to simulate hundreds of conformance streams to make sure that the chip is ready to ship. In the wireless handheld SOC space, firmware is key. Ultimately, the device must boot Linux and run a Java application on its LCD screen. Designers of network routers need to stress their chips through pseudo-random traffic to benchmark key performance metrics, such as packet drop rate. All these tasks have one thing in common: they require billions of cycles of simulation. Until designers realize that they can't manage billions of cycles like any other simulation, they hit a wall called the "Billion-Cycle Challenge." Space at this must-see seminar is limited, so register now at: Seminar Schedule 8:45am - 9am Registration, Breakfast 9am - 9:45am Debugging billion-cycle simulations: using a multi-level approach combining software debug of embedded applications, signal-level hardware debug and transaction-level monitors 9:45am - 10:15am A step-by-step guide on building system-level testbenches using virtual components and TLM that can sustain a design over billions of cycles and reach validation closure faster 10:15am - 10:30am Break 10:30am - 11am Guest speaker: experiences in overcoming the billion cycle challenge 11am - 11:30am Live demo: see the actual debug of a Linux boot sequence, when chasing HW/SW bugs in a peripheral device. Is it a software bug or a hardware bug? How can the HW and SW teams work hand-in-hand? 11:30am - 11:45am The latest ARM-based SOCs present new verification challenges. Learn about a co-emulation strategy that supports the latest processor advances. 11:45am - 12:00pm Interactive tutorial: should you care about price-per-cycle? Evaluate the best simulation engine using the "price per cycle" metrics and learn how it impacts your verification methodology 12:15pm - 12:45pm Lunch Who should attend: Hardware designers and managers in charge of verification and validation Firmware and software engineers that use pre-silicon models and prototypes Contact: EVE-USA, Inc. 2518 Mission College Blvd Santa Clara, CA 95054 (408) 855-3200 =============================================================================== You are subscribed as [_EMAIL_]. If you no longer want to receive news from our EDA sponsors but want to continue receiving other EDA newsletters, please visit Otherwise, if your email client supports HTML, please change your format preference to "HTML" for the best viewing experience. To change your personalized CafeNews mailing subscription, go to Copyright (c) 2020. Internet Business Systems, Inc. All rights reserved