You are receiving this email as a Internet Business Systems subscriber on behalf of Mentor Graphics
As clock frequencies and data rates soar, digital designers are being forced to account for the effects of degraded high-frequency signals, causing otherwise healthy bit streams to be unrecognizable at receiver ICs.
This technical forum will focus on simulation-based signal-integrity analysis of multi-gigabit interconnects. Methodologies for understanding and proactively dealing with multi-gigabit interconnect problems will be discussed, as well as future trends in IC technology.
Seminar attendees will gain a clear understanding of the following multi-gigabit design topics:

· Eye-diagram and jitter analysis using multi-bit stimuli
· Lossy-line and advanced via modeling
· Inter-symbol interference
· Integrated simulation with both HSPICE and IBIS
· Multi-gigabit system verification with Mentor Graphics ICX™ and HyperLynx GHz™
Reserve your seat and sign up today >>
View the complete PCB technical paper library >>

You are registered as: [_EMAIL_].

CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe from sponsor newsletter.

Copyright © 2020, Internet Business Systems, Inc. — 25 North 14th Steet, Suite 710 San Jose, CA 95112 — +1 (408) 882-6554 — All rights reserved.