Join Our Upcoming Free Live Webinar:

UCIe PHY Modeling and Simulation with XMODEL

June 29, 2023 14:00–15:30 Pacific Time

Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models for the physical layer (PHY) of Universal Chiplet Interconnect Express (UCIe) interface, an emerging open industry standard for chiplet interconnects. The presented UCIe PHY model includes both the analog circuits in the electrical layer and digital FSMs in the logical layer and can be simulated efficiently in SystemVerilog, using Scientific Analog’s XMODEL.

We invite everyone who is interested in the design and verification of UCIe PHY for chiplets. For analog circuit designers, the presented models will help understand the requirements posed on each circuit block, such as the scaling of bandwidth to support the link speeds ranging from 4 to 32GT/s. For digital verification engineers, the presented testbenches will illustrate how one can perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly, everyone can learn how various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets!

Jaeha Kim

C.E.O. & Founder, Scientific Analog, Inc., Palo Alto, CA
Professor, Seoul National University, Korea

Jaeha Kim is CEO and founder of Scientific Analog, Inc., Palo Alto, CA and Professor at Seoul National University (SNU), Seoul, Korea. With a flagship product called XMODEL, he is pursuing ways to make analog design and verification as efficient as digital. Dr. Kim received the B.S. degree from SNU in 1997, and the M.S. and Ph.D. degrees from Stanford University in 1999 and 2003, respectively. Prior to joining SNU, Dr. Kim was with Stanford University as Acting Assistant Professor and with Rambus, Inc. as Principal Engineer. Prof. Kim is a recipient of the Takuo Sugano award for Outstanding Far-East Paper at 2005 ISSCC and is cited as Top 100 Technology Leader of Korea by the National Academy of Engineering of Korea in 2020.