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Virtual Silicon’s 0.13µm Standard Cells at TSMC offer 20% less area with the same high performance!

When you design using Virtual Silicon’s 0.13µm Standard Cells at TSMC, you will get the same high performance you have come to expect from the 0.13µm process in a smaller footprint. This translates to:
  • More die per wafer delivering a lower cost

  • Smaller die, requiring less power

  • Fewer transistors, increasing reliability

Don’t take our word for it – try it yourself

Some of the benefits of Virtual Silicon’s Standard Cells include:

  • Each of the Virtual Silicon standard cells has been accurately modeled for both timing and power and fully verified in silicon for ease of manufacturability.

  • Virtual Silicon's cell characterization and modeling flow is the most advanced in the industry and produces the most accurate results.

We challenge you! Take a look at Virtual Silicon’s Standard Cells, register to download Virtual Silicon’s 0.13µm Standard Cell IP at TSMC to review the data and see for yourself.

For more information on Virtual Silicon and its full line of PLL, Basic I/O, Application Specific I/O and Standard Cell libraries, please visit Virtual

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